Showing papers by "Emmanuel Dubois published in 2003"

Formation of platinum-based silicide contacts: Kinetics, stoichiometry, and current drive capabilities

Abstract: A detailed analysis of the formation of Pt 2 Si and PtSi silicides is proposed, based on x-ray photoelectron spectroscopy ~XPS!, transmission electron microscopy ~TEM!, and electrical characterizations. Published kinetics of the Pt 2 Si and PtSi transformations under ultrahigh vacuum condition are consolidated on the basis of XPS measurements performed during an in situ annealing at a constant heating rate. At room temperature, an incomplete PtxSi reaction is clearly identified by XPS depth profiling. Using rapid thermal annealing at 300, 400, and 500 °C, the sequential Pt‐Pt2Si‐PtSi reaction chain is found to be completed within 2 min. Outdiffusion of silicon to the top surface is shown to be responsible for the formation of a thin SiO2 capping layer at 500 °C. Pileup of oxygen occurring at the Pt2Si/Pt reaction front is clearly identified as an inhibiting factor of the silicidation mechanism. Another incomplete reaction scheme limited to the unique formation of Pt2Si is exemplified in the case of ultra thin silicon-on-insulator films. Finally, current drive measurements on PtSi Schottky contacts have allowed us to identify 300 °C as the optimum annealing temperature while TEM cross sections demonstrate the formation of a smooth and continuous PtSi/Si interface at 300 °C. © 2003 American Institute of Physics. @DOI: 10.1063/1.1605817#

Very low Schottky barrier to n-type silicon with PtEr-stack silicide

Abstract: We investigate Er silicide formed on n-type silicon. In order to protect the Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at temperatures lower than 700 degreesC. We find that silicidation process is fully completed by rapid thermal annealing at 500 degreesC. A simplified method of analysis considering the final Schottky barrier MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low apparent Schottky barrier (smaller than 0.1 eV) on a n-type silicon substrate with a concentration of 1.4 x 10(16) cm(-3) in the active region has been obtained. (C) 2003 Elsevier Ltd. All rights reserved.

Very low Schottky barrier to N-type silicon with PtEr-stack silicide

Abstract: We investigate Er silicide formed on n-type silicon. In order to protect Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprisingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at 600iC. A simplified method of analysis considering the final Schottky-barrier SOI-MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low Schottky barrier (smaller than 0.1eV) on a n-type silicon substrate with a concentration of 1.4x10 16 cm -3 in the active region has been obtained.

Very low Schottky barrier to n-type silicon with PtEr-stack silicide

Abstract: We investigate Er silicide formed on n-type silicon. In order to protect Er from oxidation during the formation of Er silicide in non-UHV conditions, a Pt layer is deposed successively on top of Er layer. Surprinsingly, we observe that Pt remains essentially unaffected in the formation of Er silicide at 600°C. A simplified method of analysis considering the final Schottky-barrier SOI-MOSFET application has been used to characterize the Schottky barrier of the PtEr-stack silicide system. A very low Schottky barrier (smaller than 0.1eV) on a n-type substrate with a concentration of 1.4x10exp.16 cm³ in the active region has been obtained.

Accurate modeling of large angle tilt and pure vertical implantations: application to the simulation of n- and p-LDMOS backgates

Abstract: The lateral and vertical extensions of the backgate of complementary laterally diffused metal oxide semiconductor (LDMOS) are simulated. The importance of channeling for a large-angle tilt implantation and a purely vertical (0/spl deg/) implantation are studied with the atomistic simulator Crystal-TRIM. The three-dimensional (3-D) nature of the large-angle tilt implantation is transposed to two dimensions through the introduction of a pseudo-tilt angle. Both the concept of pseudo-tilt angle and the channeling effects have been integrated in the two-dimensional (2-D) process and device simulator IMPACT. These model improvements give a quantitative agreement of doping profiles and sheet resistances with experiments, and therefore provide a reliable basis for the development of n- and p-LDMOS technologies.

Performance of Pt-based Low Schottky Barrier Silicide Contacts on Weakly Doped Silicon

Abstract: One of the grand challenge imposed by CMOS down-scaling is the optimisation of the source/drain (S/D) architecture, e.g., dopant activation above solid solubility, steep dopant profiling, low silicide specific contact resistivity. Recently, the concept of very low Schottky barrier S/D MOSFET has emerged as a possible alternative to conventional architecture using highly doped S/D and midgap silicide ohmic contacts. For p-MOSFETs integration, platinum silicide is an excellent candidate because of its very low barrier to holes. This enables the use of a weakly doped substrate that inherently solves the aforementioned challenges due to highly doped S/D. This paper proposes a detailed study of the platinum silicidation reaction obtained by rapid thermal annealing. The analysis is based on X-ray photoemission spectroscopy (XPS), transmission electron miscrocopy (TEM) and low temperature-dependent current-voltage measurements. Using XPS analysis, it is shown that: i) an initial silicide layer is formed at room temperature, ii) three stable phases Pt, Pt2Si, PtSi can not coexist providing that iii) the annealing ambience is strictly controlled to avoid the formation of a SiO2 barrier due to oxygen penetration into the platinum overlayer. Starting from an initial 15 nm thick Pt layer subsequently annealing at 300°C, TEM cross-sections reveal that homogeneous 32 nm PtSi layers with a uniform grain size distribution are formed. Finally, current-voltage characteristics have been measured on a special test structure that accounts for the lateral disposition of S/D regions in a typical MOSFET architecture. It consists in two back-to-back Schottky contacts separated by a narrow silicon gap both on bulk silicon and Silicon-On-Insulator (SOI) substrates. Based on temperature-dependent electrical measurements (Arrhenius plot), it is shown that field emission is involved in the current transport mechanism, in addition to thermionic emission. An excellent current drive performance of 220 μA per micron width has been obtained for a 45 nm silicon gap on a 10 nm thick SOI substrate.