The move to implement metal oxide based gate dielectrics in a metal-oxide-semiconductor field effect transistor is considered one of the most dramatic advances in materials science since the invention of silicon based transistors. Metal oxides are superior to SiO 2 in terms of their higher dielectric constants that enable the required continuous down-scaling of the electrical thickness of the dielectric layer while providing a physically thicker layer to suppress the quantum mechanical tunneling through the dielectric layer. Over the last decade, hafnium based materials have emerged as the designated dielectrics for future generation of nano-electronics with a gate length less than 45 nm, though there exists no consensus on the exact composition of these materials, as evolving device architectures dictate different considerations when optimizing a gate dielectric material. In addition, the implementation of a non-silicon based gate dielectric means a paradigm shift from diffusion based thermal processes to atomic layer deposition processes. In this report, we review how HfO 2 emerges from all likely candidates to become the new gold standard in the microelectronics industry, its different phases, reported electrical properties, and materials processing techniques. Then we use specific examples to discuss the evolution in designing hafnium based materials, from binary to complex oxides and to non-oxide forms as gate dielectric, metal gates and diffusion barriers. To address the impact of these hafnium based materials, their interfaces with silicon as well as a variety of semiconductors are discussed. Finally, the integration issues are highlighted, including carrier scattering, interface state passivation, phonon engineering, and nano-scale patterning, which are essential to realize future generations of devices using hafnium-based high- k materials.

Development of hafnium based high-k materials—A review

The deposition of Al 2 O 3 by remote plasma atomic layer deposition (ALD) in the Oxford Instruments FlexAL reactor was studied and compared with results from thermal ALD in the same reactor. Trimethylaluminum [Al(CH 3 ) 3 ] was used as the metal precursor and O 2 plasma and H 2 O were used as oxidizing agents for the plasma and thermal processes, respectively. For remote plasma ALD with a total cycle time of 4 s, the growth per cycle decreased monotonically with substrate temperature, from 1.7 A/cycle at 25°C to 1.0 A/cycle at 300°C. This growth per cycle was consistently higher than that obtained for thermal ALD. For the latter a maximum growth per cycle of ∼ 1.0 A/cycle was found at 200°C. The film properties investigated were nearly independent of oxidant source for temperatures between 100 and 300°C, with a slightly higher mass density for the remote plasma ALD Al 2 O 3 films. Films deposited at 200 and 300°C were stoichiometric with a mass density of 3.0 g/cm 3 and low C (< 1 atom %) and H (<3 atom %) contents. At lower substrate temperatures, oxygen-rich films were obtained with a lower mass density and higher H-content. Remote plasma ALD produced uniform Al 2 O 3 films with nonuniformities of less than ±2% over 200 mm diam substrates. Excellent conformality was obtained for films deposited in macropores with an aspect ratio of ∼8 (2.0-2.5 μm diam). Preliminary results on electrical properties of remote plasma deposited films showed high dielectric constants of 7.8 and 8.9 for as-deposited and forming gas annealed Al 2 O 3 , respectively.

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Plasma and thermal ALD of Al2O3 in a commercial 200 mm ALD reactor

Atomic layer deposition of titanium nitride from TDMAT precursor

The authors describe a remote plasma atomic layer deposition reactor (Oxford Instruments FlexAL™) that includes an inductively coupled plasma source and a load lock capable of handling substrates up to 200mm in diameter. The deposition of titanium nitride (TiN) and hafnium oxide (HfO2) is described for the combination of the metal-halide precursor TiCl4 and H2–N2 plasma and the combination of the metallorganic precursor Hf[N(CH3)(C2H5)]4 and O2 plasma, respectively. The influence of the plasma exposure time and substrate temperature has been studied and compositional, structural, and electrical properties are reported. TiN films with a low Cl impurity content were obtained at 350°C at a growth rate of 0.35A∕cycle with an electrical resistivity as low as 150μΩcm. Carbon-free (detection limit <2at.%) HfO2 films were obtained at a growth rate of 1.0A∕cycle at 290°C. The thickness and resisitivity nonuniformity was <5% for the TiN and the thickness uniformality was <2% for the HfO2 films as determined over 20...

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Deposition of TiN and HfO{sub 2} in a commercial 200 mm remote plasma atomic layer deposition reactor

Titanium nitride (TiN) films were deposited by a plasma-assisted atomic layer deposition (PA-ALD) process, based on TiCl 4 precursor dosing and remote H 2 -N 2 plasma exposure, at temperatures ranging from 100 to 400°C. The plasma, the PA-ALD process, and the resulting TiN material properties were extensively investigated. The plasma was studied by optical emission spectroscopy and Langmuir probe, revealing an ion density of 10 9 cm -3 and an electron temperature of 3.5 eV just above the substrate. Under floating conditions there is thus a considerable ion flux towards the substrate per ALD cycle with a typical ion energy of ∼ 15 eV. TiN film growth was studied by in situ spectroscopic ellipsometry, revealing self-limiting surface reactions for the complete temperature range. At 100°C the growth rate of 0.3 A/cycle was found to be significantly lower than the growth rate of 0.6 A/cycle at 400°C. The stoichiometry of the films varied with the plasma exposure time, while the Cl content was mostly affected by the deposition temperature (2.1 atom % at 100°C to 0.07 atom % at 400°C). Resistivities as low as 71 μΩ cm were obtained at a temperature of 400°C, while at 100°C a fair resistivity of 209 μΩ cm was reached. These results show that PA-ALD with TiCl 4 and H 2 -N 2 plasma is well suited for low-temperature deposition of high-quality TiN films.

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Low-Temperature Deposition of TiN by Plasma-Assisted Atomic Layer Deposition

The architecture, materials choice and process technology for stacked-capacitors in embedded-DRAM applications are a crucial concern for each new technology node. An overview of the evolution of capacitor technology is presented from the early days of planar PIS (poly/insulator/silicon) capacitors to the MIM (metal/insulator/metal) capacitors used for todays 65 nm technology node. In comparing Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in 65 nm eDRAM technology, Al2O3 is found to give a good compromise between capacitor performance and manufacturability. The use of atomic layer deposition (ALD) is identified to be an enabling technology for both high-k dielectrics and capacitor electrodes. � 2005 Elsevier Ltd. All rights reserved.

Evolution of materials technology for stacked-capacitors in 65 nm embedded-DRAM

Spike anneal: RTP processing at reduced thermal budget with applications to TiSi 2 formation towards 0.1-mm linewidths

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Surface modification of metals by ion implantation

The integrated circuit comprises lateral isolation regions formed at the sides of at least one projecting polysilicon region so as to be in contact therewith, said lateral isolation regions each being composed of a smaller isolation layer (402), which is in contact with said projecting region (2), and of a larger isolation layer (411), and it further comprises a zone (5) including a metal silicide situated in the upper part of the polysilicon region (2). Each lateral isolation region comprises a vertical trench (TR) made in the smaller isolation layer (402) between the larger isolation layer (411) and the corresponding side (F) of the projecting region (2), said trench (TR) extending from the top of the larger isolation layer (411) of the corresponding lateral isolation region down to a predetermined depth (h).

Salicide process for mosfet integrated circuit

Le circuit integre comprend des regions d'isolation laterales accolees aux flancs d'au moins une region saillante de polysilicium et formees chacune d'une couche isolante inferieure (402) au contact de ladite zone saillante (2) et d'une couche isolante superieure (411), et une zone (5) comportant un siliciure de metal situe dans la partie superieure de la region de polysilicium (2). Chaque region d'isolation laterale comporte une tranchee verticale (TR) menagee dans la couche isolante inferieure (402) entre la couche isolante superieure (411) et le flanc correspondant (F) de la region saillante (2), cette tranchee (TR) s'etendant depuis le sommet de la couche isolante superieure (411) de la region d'isolation laterale correspondante sur une profondeur predeterminee (h).

Eric Gerritsen

Papers

Evolution of materials technology for stacked-capacitors in 65 nm embedded-DRAM

Spike anneal: RTP processing at reduced thermal budget with applications to TiSi 2 formation towards 0.1-mm linewidths

Surface modification of metals by ion implantation

Salicide process for mosfet integrated circuit

Procede de fabrication d'un circuit integre comportant une siliciuration amelioree et circuit integre correspondant