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Eric Sprangle
Researcher at Intel
Publications - 24
Citations - 1820
Eric Sprangle is an academic researcher from Intel. The author has contributed to research in topics: Cache pollution & Cache. The author has an hindex of 12, co-authored 24 publications receiving 1805 citations.
Papers
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Journal ArticleDOI
Larrabee: a many-core x86 architecture for visual computing
Larry D. Seiler,Doug Carmean,Eric Sprangle,Tom Forsyth,Michael Abrash,Pradeep Dubey,Stephen Junkins,Adam T. Lake,Jeremy Sugerman,Robert Dale Cavin,Roger Espasa,Ed Grochowski,Toni Juan,Pat Hanrahan +13 more
TL;DR: This article consists of a collection of slides from the author's conference presentation, some of the topics discussed include: architecture convergence; Larrabee architecture; and graphics pipeline.
Journal ArticleDOI
Larrabee: A Many-Core x86 Architecture for Visual Computing
Larry D. Seiler,Douglas M. Carmean,Eric Sprangle,Tom Forsyth,Pradeep Dubey,Stephen Junkins,Adam T. Lake,Robert Dale Cavin,Roger Espasa,Edward T. Grochowski,Toni Juan,Michael Abrash,Jeremy Sugerman,Pat Hanrahan +13 more
TL;DR: The Larrabee many-core visual computing architecture uses multiple in-order x86 cores augmented by wide vector processor units, together with some fixed-function logic, which increases the architecture's programmability as compared to standard GPUs.
Journal ArticleDOI
Increasing processor performance by implementing deeper pipelines
Eric Sprangle,Doug Carmean +1 more
TL;DR: It is shown that in the same process technology, designing deeper pipelines can increase the processor frequency by 100%, which, when combined with larger on-chip caches can yield performance improvements of 35% to 90% over a Pentium® 4 like processor.
Patent
Methods, apparatus, and instructions for converting vector data
TL;DR: In this paper, a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register is described.
Proceedings ArticleDOI
Enabling scalability and performance in a large scale CMP environment
Bratin Saha,Ali-Reza Adl-Tabatabai,Anwar Ghuloum,Mohan Rajagopalan,Richard L. Hudson,Leaf Petersen,Vijay Menon,Brian R. Murphy,Tatiana Shpeisman,Eric Sprangle,Anwar Rohillah,Doug Carmean,Jesse Fang +12 more
TL;DR: This paper presents the architecture of McRT and discusses the experiences with the system, including experimental evaluation that lead to several interesting, non-intuitive findings, providing key insights about the structure of the system stack at this scale.