Journal ArticleDOI
A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor
Andre Vandemeulebroecke,Etienne Vanzieleghem,T. Denayer,Charles Trullemans,Paul Jespers +4 more
- Vol. 25, Iss: 3, pp 748-756
TLDR
A carry-free division algorithm is described based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder.Abstract:
A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder. Its application to a 1024-b RSA (Rivest, Shamir, and Adelman) cryptographic chip is presented. The features of this new algorithm allowed high performance (8 kb/s for 1024-b words) to be obtained for relatively small area and power consumption (80 mm/sup 2/ in a 2- mu m CMOS process and 500 mW at 25 MHz). >read more
Citations
More filters
Journal ArticleDOI
Optimal left-to-right binary signed-digit recoding
Marc Joye,Sung-Ming Yen +1 more
TL;DR: New methods for producing optimal binary signed-digit representations that are useful in the fast computation of exponentiations are described, contrary to existing algorithms, which are scanned from left to right.
Journal ArticleDOI
The differential CORDIC algorithm: Constant scale factor redundant implementation without correcting iterations
H. Dawid,Heinrich Meyr +1 more
TL;DR: It is proved that, due to the lack of additional operations, DCORDIC compares favorably with the previously known redundant methods in terms of latency and computational complexity.
Proceedings ArticleDOI
High-radix modular multiplication for cryptosystems
TL;DR: Two algorithms for modular multiplication with very large moduli are analyzed specifically for their applicability when a high radix is used for the multiplier.
Journal ArticleDOI
A radix-4 modular multiplication hardware algorithm for modular exponentiation
TL;DR: A fast radix-4 modular multiplication hardware algorithm is proposed, efficient for modular exponentiation with a large modulus, used in public-key cryptosystems such as the RSA cryptos system and suitable for VLSI implementation.
Journal ArticleDOI
A fast VLSI adder architecture
H.R. Srinivas,Keshab K. Parhi +1 more
TL;DR: The proposed adder, referred to as the sign-select conversionAdder, is faster than all previous high-speed two's-complement binary adders for large word lengths and is very well suited for VLSI implementation.
References
More filters
Journal ArticleDOI
Signed-Digit Numbe Representations for Fast Parallel Arithmetic
TL;DR: Sign-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff are discussed.
Book
The first ten years of public-key cryptography
TL;DR: The development of public-key cryptography is described in this article, and its principles are elucidated, including exponential key exchange, the trap-door knapsack public key cryptosystem, the Rivest-Shamir-Adleman (RSA) system, and the breaking of the Knapsack Cryptosystem.
Proceedings ArticleDOI
Design of high speed MOS multiplier and divider using redundant binary representation
TL;DR: This work improved the algorithm and the method of implementation, and designed an advanced multiplier and divider for MOS LSI based on a new algorithm that has several excellent features such as high speed addition operations.
Journal ArticleDOI
The first ten years of public-key cryptography
TL;DR: The discussion covers exponential key exchange, the trap-door knapsack public-key cryptosystem, the Rivest-Shamir-Adleman (RSA) system, and the breaking of theknapsack cryptos system.