Spintronics, or spin electronics, involves the study of active control and manipulation of spin degrees of freedom in solid-state systems. This article reviews the current status of this subject, including both recent advances and well-established results. The primary focus is on the basic physical principles underlying the generation of carrier spin polarization, spin dynamics, and spin-polarized transport in semiconductors and metals. Spin transport differs from charge transport in that spin is a nonconserved quantity in solids due to spin-orbit and hyperfine coupling. The authors discuss in detail spin decoherence mechanisms in metals and semiconductors. Various theories of spin injection and spin-polarized transport are applied to hybrid structures relevant to spin-based devices and fundamental studies of materials properties. Experimental work is reviewed with the emphasis on projected applications, in which external electric and magnetic fields and illumination by light will be used to control spin and charge dynamics to create new functionalities not feasible or ineffective with conventional electronics.

/pdf/spintronics-fundamentals-and-applications-2dx38n6phu.pdf

Spintronics: Fundamentals and applications

1. Introduction and overview 2. Film stress and substrate curvature 3. Stress in anisotropic and patterned films 4. Delamination and fracture 5. Film buckling, bulging and peeling 6. Dislocation formation in epitaxial systems 7. Dislocation interactions and strain relaxation 8. Equilibrium and stability of surfaces 9. The role of stress in mass transport.

Thin Film Materials: Stress, Defect Formation and Surface Evolution

Field-effect transistors (FETs) based on semi-conductor nanowires could one day replace standard silicon MOSFETs in miniature electronic circuits. MOSFETs, or metal-oxide semiconductor field-effect transistors, are a type of transistor used for high-speed switching and in a computer's integrated circuits. A specially designed nanowire with a germanium shell and silicon core has shown promise as a nanometre-scale field-effect transistor: it has a near-perfect channel for electronic conduction. Now, in transistor configuration, this germanium/silicon nanowire is shown to have properties including high conductance and short switching time delay that are better than state-of-the-art silicon MOSFETs. In a transistor configuration, a new germanium/silicon nanowire has characteristics such as conductance, on-current and switching time delay that are better than those of state-of-the-art silicon metal-oxide-semiconductor field-effect transitors. Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.

Ge/Si nanowire heterostructures as high-performance field-effect transistors

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

/pdf/device-scaling-limits-of-si-mosfets-and-their-application-299ftwsxth.pdf

Device scaling limits of Si MOSFETs and their application dependencies

The past decade has seen rapid progress in research into high-performance Ge-on-Si photodetectors. Owing to their excellent optoelectronic properties, which include high responsivity from visible to near-infrared wavelengths, high bandwidths and compatibility with silicon complementary metal–oxide–semiconductor circuits, these devices can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and infrared imaging at low cost and low power consumption. This Review summarizes the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors. Owing to their excellent optoelectronic properties, Ge-on-Si photodetector can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and low-cost infrared imaging at low power consumption. This Review covers the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors.

High-performance Ge-on-Si photodetectors

Water purification system comprising filtration media sized with respect to each other to allow a first contaminant in the water to saturate the first medium with a delay prior to saturation of the second medium with a second contaminant.

Water purification and enhancement systems

Deep level traps in the low dislocation density, 5.1 × 107 cm−2, semi-polar GaN (11–22), grown on patterned sapphire substrate was characterized for the first time using deep level transient spectroscopy (DLTS) and deep level optical spectroscopy (DLOS). DLTS revealed two deep levels ET1 = EC − 0.24 eV and ET2 = EC − 0.41 eV in the semi-polar GaN layer. The dominant trap ET1 = EC − 0.24 eV with a density of 6.1 × 1014 cm−3, is documented in c-plane and m-plane GaN. It is attributed to VN. DLOS revealed two deep level traps ET3 = EC − 1.20 eV and ET4 = EC − 3.26 eV. The dominant level ET4 = EC − 3.26 eV is also observed in non-polar m-plane GaN grown on sapphire and it is attributed to CN acceptor-like state. The total trap density of the semi-polar GaN is about 2 × 1016 cm−3, which is comparable with that found in c-plane GaN.

Deep level traps in semi-polar n-GaN grown on patterned sapphire substrate by metalorganic vapor phase epitaxy

The objective of this work was to develop an improved wet etch-stop technology for silicon micromachining. To establish a reference for process improvement, the diffusion process currently used to fabricate p ++ Si:B etch stops was comprehensively investigated. Subsequently, a novel germanium- based epitaxial etch-stop technology was developed. A range of techniques were used to study p ++ silicon layers created by boron diffusion into (001) silicon wafers. The results revealed gradients in boron and lattice constant, as well as a graded three- dimensional dislocation array from lattice-mismatch stress. The gradients in boron concentration and dislocation density can lead to curl in micromachined structures. Although annealing steps can remove the boron gradient, a flat membrane will be a tenuous balance. Epitaxial films of p ++ Si:B and strain-compensated p ++ Si 1-x Ge x :B can remove composition gradients and improve process control. However, it is undesirable to depend on p -type layers doped at levels near the solubility limit to prevent etching. We have therefore developed a unique etch stop created from relaxed SiGe alloys. Etch-stop behavior quite similar to heavily boron-doped silicon has been demonstrated in undoped silicon-germanium. Neither strain nor defects are responsible for the etch-stop behavior. A model is proposed based on energy band structure and a SiO x passivation mechanism.

Silicon-Based Epitaxial Films for Mems

Erratum: “Strain relaxation due to V-pit formation in InxGa1−xN∕GaN epilayers grown on sapphire” [J. Appl. Phys. 98, 084906 (2005)]

Strain in electronic devices is receiving renewed interest due to the advantageous effects of strain on carrier mobility, and therefore drive current However, the physics of strain incorporation, by definition, introduces the physics of strain relief At typical CMOS process temperatures, semiconductors become ductile, and therefore dislocation nucleation and glide are the most common means of plastic relaxation To obtain the highest levels of strain, dislocation nucleation and propagation must be avoided It can be advantageous to create alternative lattice constants for creating strain in other regions, in which case plastic deformation is purposely created in the structure and dislocation sites must be managed If the goal for the particular device is to create completely relaxed lattice constants, we show global and local methods to control threading dislocation densities We also show methods to achieve the opposite, ie larger values of strain, higher than the level expected in equilibrium By understanding the nature of dislocation nucleation and propagation, we can overcome future dislocation engineering challenges for new materials systems such as III-V MISFIT heterostructures

Eugene A. Fitzgerald

Papers

Water purification and enhancement systems

Deep level traps in semi-polar n-GaN grown on patterned sapphire substrate by metalorganic vapor phase epitaxy

Silicon-Based Epitaxial Films for Mems

Erratum: “Strain relaxation due to V-pit formation in InxGa1−xN∕GaN epilayers grown on sapphire” [J. Appl. Phys. 98, 084906 (2005)]

Dislocation engineering in strained mos materials