Spintronics, or spin electronics, involves the study of active control and manipulation of spin degrees of freedom in solid-state systems. This article reviews the current status of this subject, including both recent advances and well-established results. The primary focus is on the basic physical principles underlying the generation of carrier spin polarization, spin dynamics, and spin-polarized transport in semiconductors and metals. Spin transport differs from charge transport in that spin is a nonconserved quantity in solids due to spin-orbit and hyperfine coupling. The authors discuss in detail spin decoherence mechanisms in metals and semiconductors. Various theories of spin injection and spin-polarized transport are applied to hybrid structures relevant to spin-based devices and fundamental studies of materials properties. Experimental work is reviewed with the emphasis on projected applications, in which external electric and magnetic fields and illumination by light will be used to control spin and charge dynamics to create new functionalities not feasible or ineffective with conventional electronics.

/pdf/spintronics-fundamentals-and-applications-2dx38n6phu.pdf

Spintronics: Fundamentals and applications

1. Introduction and overview 2. Film stress and substrate curvature 3. Stress in anisotropic and patterned films 4. Delamination and fracture 5. Film buckling, bulging and peeling 6. Dislocation formation in epitaxial systems 7. Dislocation interactions and strain relaxation 8. Equilibrium and stability of surfaces 9. The role of stress in mass transport.

Thin Film Materials: Stress, Defect Formation and Surface Evolution

Field-effect transistors (FETs) based on semi-conductor nanowires could one day replace standard silicon MOSFETs in miniature electronic circuits. MOSFETs, or metal-oxide semiconductor field-effect transistors, are a type of transistor used for high-speed switching and in a computer's integrated circuits. A specially designed nanowire with a germanium shell and silicon core has shown promise as a nanometre-scale field-effect transistor: it has a near-perfect channel for electronic conduction. Now, in transistor configuration, this germanium/silicon nanowire is shown to have properties including high conductance and short switching time delay that are better than state-of-the-art silicon MOSFETs. In a transistor configuration, a new germanium/silicon nanowire has characteristics such as conductance, on-current and switching time delay that are better than those of state-of-the-art silicon metal-oxide-semiconductor field-effect transitors. Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.

Ge/Si nanowire heterostructures as high-performance field-effect transistors

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

/pdf/device-scaling-limits-of-si-mosfets-and-their-application-299ftwsxth.pdf

Device scaling limits of Si MOSFETs and their application dependencies

The past decade has seen rapid progress in research into high-performance Ge-on-Si photodetectors. Owing to their excellent optoelectronic properties, which include high responsivity from visible to near-infrared wavelengths, high bandwidths and compatibility with silicon complementary metal–oxide–semiconductor circuits, these devices can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and infrared imaging at low cost and low power consumption. This Review summarizes the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors. Owing to their excellent optoelectronic properties, Ge-on-Si photodetector can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and low-cost infrared imaging at low power consumption. This Review covers the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors.

High-performance Ge-on-Si photodetectors

A novel method of synthesizing and controlling the size of germanium nanocrystals was developed. A tri-layer structure comprising of a thin (~5nm) SiO2 layer grown using rapid thermal oxidation (RTO), followed by a layer of Ge+SiO2 of varying thickness (6 20 nm) deposited using the radio frequency (r.f.) co-sputtering technique and a SiO2 cap layer (50nm) deposited using r.f. sputtering, was investigated. It was verified using TEM that germanium nanocrystals of sizes ranging from 6 – 20 nm were successfully fabricated after thermal annealing of the tri-layer structure under suitable conditions. The nanocrystals were found to be well confined by the RTO SiO2 and the cap SiO2 under specific annealing conditions. The electrical properties of the tri-layer structure have been characterized using MOS capacitor test devices. A significant hysteresis can be observed from the C-V measurements and this suggests the charge storage capability of the nanocrystals. The proposed technique has the potential for fabricating memory devices with controllable nanocrystals sizes.

/pdf/synthesis-of-germanium-nanocrystals-and-its-possible-29ervmv81g.pdf

Synthesis of Germanium Nanocrystals and its Possible Application in Memory Devices

Silicon-gemanium is a promising materials system for delivering near-IR photodetection on the ubiquitous silicon substrate. The 4% lattice mismatch leads to biaxial strain for SiGe films grown coherently on (100) Si substrates, which both extends the long wavelength detection limit by reducing the band gap and defines the critical thickness for the SiGe film. We have studied the use of strained-layer superlattices grown on high quality relaxed SiGe buffers. Graded buffers are ideal virtual substrates for achieving a complete range of compositions and strains for GeSi alloys. A physical model has been created to map out the absorption coefficient as a function of Ge fraction and (100) biaxial strain. Based on calculated absorption spectra as a function of composition and strain, we have designed and grown a Ge/Ge0.5Si0.5 strain-balanced superlattice on a high quality Ge0.75Si0.25 relaxed buffer using UHV-CVD. The strain-balanced superlattice has an effective absorption coefficient of 5000 cm−1. The relaxed buffer serves as a virtual substrate with relatively low threading dislocation density (106 cm-−2). The effect of the threading dislocations on the leakage current of P-I-N junctions is also investigated. Electron beam induced current (EBIC) is used to determine the dislocation density of SiGe relaxed buffer junctions grown with different grading rates. Mesa isolated devices are used to determine bulk leakage current densities for the SiGe junctions. The bulk leakage current density scales directly with the dislocation density. Bulk leakage currents density per dislocation length (2×10−5 A cml) agrees with deep level transient spectroscopy (DLTS) determined literature values for SiGe capture cross-section and defect density per dislocation in Si.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S1946427400191948

Strained SiGe Materials for High Quantum Efficiency Photodiodes at µ = 1.3 to 1.5µm

This paper presents growth, characterization and device results for III-V optoelectronic and solar cell heterostructure devices that have been monolithically integrated on Si via ultra low dislocation density SiGe interlayers. Prior work that has demonstrated high performance single junction solar cells (Andre et al., 2005) and visible wavelength LEDs (Kwon et al., 2005) on Si is extended here to include visible wavelength laser diodes and dual junction solar cells on Si in which AlGaInP materials are used as active layers on Si

III-V/Si Device Integration Via Metamorphic SiGe Substrates

Further insight into strained layer relaxation processes have been achieved in this work. Effects of surface roughness, dislocation velocities, and dislocation nucleation have been de-coupled. In order to achieve low threading dislocation density with a high degree of relaxation, we are forced to create structures that introduce a high degree of lattice mismatch at the surface, i.e. a gradient in Ge composition in thickness. Thus, the graded layer must be introduced. However, these experiments have shed further light on the design of such structures, and we have produced relaxed layers with low threading dislocation density that are 4times less thick than their control graded composition layers

Reducing Threading Dislocation Densities in SiGe Mismatched Layers by Controllingc Strainc rate and Surface Roughness

A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end. A method for the fabrication of a prestructured SOI substrate is also disclosed. The substrate has fin-shaped strips evenly distributed over the entire surface.

Eugene A. Fitzgerald

Papers

Synthesis of Germanium Nanocrystals and its Possible Application in Memory Devices

Strained SiGe Materials for High Quantum Efficiency Photodiodes at µ = 1.3 to 1.5µm

III-V/Si Device Integration Via Metamorphic SiGe Substrates

Reducing Threading Dislocation Densities in SiGe Mismatched Layers by Controllingc Strainc rate and Surface Roughness

Finfet device and method to make same