Power has become the primary design constraint for chip designers today. While Moore's law continues to provide additional transistors, power budgets have begun to prohibit those devices from actually being used. To reduce energy consumption, voltage scaling techniques have proved a popular technique with subthreshold design representing the endpoint of voltage scaling. Although it is extremely energy efficient, subthreshold design has been relegated to niche markets due to its major performance penalties. This paper defines and explores near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region retains much of the energy savings of subthreshold operation with more favorable performance and variability characteristics. This makes it applicable to a broad range of power-constrained computing segments from sensors to high performance servers. This paper explores the barriers to the widespread adoption of NTC and describes current work aimed at overcoming these obstacles.

Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits

Power has become the primary design constraint for chip designers today. While Moore's law continues to provide additional transistors, power budgets have begun to prohibit those devices from actually being used. To reduce energy consumption, voltage scaling techniques have proved a popular technique with subthreshold design representing the endpoint of voltage scaling. Although it is extremely energy efficient, subthreshold design has been relegated to niche markets due to its major performance penalties. This paper defines and explores near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region retains much of the energy savings of subthreshold operation with more favor- able performance and variability characteristics. This makes it applicable to a broad range of power-constrained computing segments from sensors to high performance servers. This paper explores the barriers to the widespread adoption of NTC and describes current work aimed at overcoming these obstacles.

Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits Future computer systems promise to achieve an energy reduction of 100 or more times with memory design, device structure, device fabrication techniques, and clocking, all optimized for low-voltage operation.

An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be designed for exceptional stability and write margins, array-level implications must also be considered to achieve a viable memory solution. These constraints can be addressed by modifying traditional 6T-SRAM techniques and conceding some design complexity and area penalties. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies. The proposed 8T solution is demonstrated in a high-performance 32 kb subarray designed in 65 nm PD-SOI CMOS that operates at 5.3 GHz at 1.2 V and 295 MHz at 0.41 V.

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

With the widespread adoption of the Internet of Things (IoT), the number of connected devices is growing at an exponential rate, which is contributing to ever-increasing, massive data volumes. Real-time analytics on the massive IoT data, referred to as the “real-time IoT analytics” in this paper, is becoming the mainstream with an aim to provide an immediate or non-immediate actionable insights and business intelligence. However, the analytics network of the existing IoT systems does not adequately consider the requirements of the real-time IoT analytics. In fact, most researchers overlooked an appropriate design of the IoT analytics network while focusing much on the sensing and delivery networks of the IoT system. Since much of the IoT analytics network has often been taken as granted, the survey, in this paper, we aim to review the state-of-the-art of the analytics network methodologies, which are suitable for real-time IoT analytics. In this vein, we first describe the basics of the real-time IoT analytics, use cases, and software platforms, and then explain the shortcomings of the network methodologies to support them. To address those shortcomings, we then discuss the relevant network methodologies which may support the real-time IoT analytics. Also, we present a number of prospective research problems and future research directions focusing on the network methodologies for the real-time IoT analytics.

A Survey on Network Methodologies for Real-Time Analytics of Massive IoT Data and Open Research Issues

Circuit blocks for a 1.5 mm3 microsystem enable continuous monitoring of intraocular pressure. Due to power and form-factor limitations, circuit blocks are designed at nanowatt power levels not completely explored before. The system includes a 75% efficient 90 nW DC-DC converter which is the most efficient reported sub- μW converter in literature. It also includes a novel 4.7 nJ/bit FSK radio that achieves 10 cm of transmission range at 10 -6 BER which is also the lowest number reported for short-range through-tissue wireless links for biomedical implants. A MEMS capacitive sensor and ΣΔ capacitance-to-digital converter measure IOP with 0.5 mmHg accuracy. A microcontroller processes and saves IOP data and stores it in a 2.4 fW/bitcell SRAM. The microsystem harvests a maximum power of 80 nW in sunlight with a light irradiance of 100 mW/cm2 AM 1.5 from an integrated 0.07 mm2 solar cell to recharge a 1 mm2 1 μAh thin-film battery and power the load circuits. The design achieves zero-net-energy operation with 1.5 hours of sunlight or 10 hours of bright indoor lighting daily.

Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor

A 32 kb subarray demonstrates practical implementation of a 65 nm node 8T-SRAM cell for variability tolerance in highspeed caches. Ideal cell stability allows single-supply operation down to 0.41 V at 295 MHz without dynamic voltage techniques. Despite a larger cell, array area is competitive with 6T-SRAM due to higher array efficiency. With an LSDL decoder, a gated diode sense amplifier, and design tradeoffs enabled by the 8 T cell, 5.3 GHz operation at 1.2 V is achieved.

A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS

Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each of the cells. During a READ operation the eDRAM cell releases its charge indicating its digital state. The digital charge propagates through the eDRAM sense amplifier circuitry to a mid-rail amplifier inverter circuit which amplifies the charge and provides it to a latch circuit. The latch circuit, in turn, inverts the charge to correctly represent at its output the logical value stored in the eDRAM cell being read, and returns the charge through the eDRAM sense amplifier circuitry to replenish the eDRAM cell.

High Performance eDRAM Sense Amplifier

Techniques for managing big data include retrieval using per-subject dictionaries having multiple levels of sub-classification hierarchy within the subject. Entries may include subject-determining-power (SDP) scores that provide an indication of the descriptive power of the entry term with respect to the subject of the dictionary containing the term. The same term may have entries in multiple dictionaries with different SDP scores in each of the dictionaries. A retrieval request for one or more documents containing search terms descriptive of the one or more documents can be processed by identifying a set of candidate documents tagged with subjects, i.e., identifiers of per-subject dictionaries having entries corresponding to a search term, then using affinity values to adjust the aggregate score for the terms in the dictionaries. Documents are then selected for best match to the subject based on the adjusted scores. Alternatively, the adjustment may be performed after selecting the documents by re-ordering them according to adjusted scores.

Document retrieval using internal dictionary-hierarchies to adjust per-subject match results

Low-voltage, single-ended (SE) potentiostats are unable to detect many analytes of interest because the oxidation potentials of these analytes are greater than the voltage that the potentiostat can deliver to the electrodes. In this work, a fully-differential (FD) potentiostat is described which enables detection of a wide range of analytes using a supply voltage of 1.8 V. The FD potentiostat was implemented in TSMC's 0.18 mum CMOS process and has been verified experimentally. A theoretical discussion of the FD potentiostat is given and comparisons to SE potentiostats are provided. Biological and environmental analytes are chemically detected using the FD potentiostat.

A Fully Differential Potentiostat

Amperometric chemical sensing systems implemented in deep-submicron processes can meet the dimensional and functional requirements for bio-implantable and remote sensing applications. The low-voltage nature of these processes, however, limits the functionality of the sensor's electronic interface, the potentiostat. A new, fully-differential (FD) potentiostat that mitigates these problems is presented. The FD potentiostat was implemented in TSMC's 0.18 /spl mu/m CMOS process and experimentally verified. The circuit maintains full functionality while operating at half the supply voltage of standard architectures. Analytes of biological and environmental importance are chemically analyzed using the FD potentiostat. Results indicate that the FD potentiostat enables system-on-chip sensor technology which may one day lead to pervasive sensing.

Fadi H. Gebara

Papers

A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS

High Performance eDRAM Sense Amplifier

Document retrieval using internal dictionary-hierarchies to adjust per-subject match results

A Fully Differential Potentiostat

A low-voltage, chemical sensor interface for systems-on-chip: the fully-differential potentiostat