Fauziyah Salehuddin

TL;DR: In this paper, the influence of process parameters such as HALO and Source/Drain (S/D) Implantation on threshold voltage (VTH) in Complementary Metal Oxide Semiconductor (CMOS) technology using Taguchi Method.

TL;DR: In this paper, the performance analysis of several different high-k dielectrics technology with tungsten silicide (WSix) as a metal-gate in ultrathin pillar vertical double-gate (DG) NMOS architecture is presented.

TL;DR: In this paper, an investigation on the impact of different dose, energy and tilt angle of S/D implantation towards threshold voltage (VTH) value in vertical double-gate PMOS device was conducted by using L8 2k-factorial design.

Abstract: This present study focuses on finding the optimal process parameters, considering multiple electrical properties of titanium dioxide/tungsten silicide (TiO 2 /WSi x )-based vertical double-gate MOSFET via L 9 orthogonal array (OA) Taguchibased grey fuzzy logic. Four process parameters that are V TH implant energy, halo implant dose, source/drain (S/D) implant dose and S/D implant tilt angle, are optimized to obtain the most desired value of on-current (I ON ), off-current (IOFF ) and subthreshold slope (SS). The design of experiment (DoE) is based on the L 9 OA of Taguchi method and the experimental value for multiple electrical characteristics are represented by a grey fuzzy reasoning grade (GFRG). The most optimal level of four process parameters towards I ON , IOFF and SS are chosen based on the highest GFRG. The results of analysis of variance (ANOVA) show that the most dominant process parameter is S/D implant tilt angle with 96.76% factor effect on GFRG. The most optimal value for ION , IOFF and SS after the optimization are 1589.2 µA/µm, 8.483E-10 A/µm and 68.21 mV/dec respectively with 0.564 of GFRG.

TL;DR: In this article, the vertical double gate architecture of MOSFET device with ultrathin Si- pillar was introduced by keeping both silicon dioxide (SiO 2 ) and polysilicon as the main materials.