Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.

https://hal.archives-ouvertes.fr/hal-03421528/document

GaN-based power devices: Physics, reliability, and perspectives

https://eprints.lib.hokudai.ac.jp/dspace/bitstream/2115/68840/1/1-s2.0-S1369800117317304-main.pdf

State of the art on gate insulation and surface passivation for GaN-based power HEMTs

We report a high-performance normally-off Al2O3/AlN/GaN MOS-channel-high electron mobility transistor (MOSC-HEMT) featuring a monocrystalline AlN interfacial layer inserted between the amorphous Al2O3 gate dielectric and the GaN channel. The AlN interfacial layer effectively blocks oxygen from the GaN surface and prevents the formation of detrimental Ga-O bonds. Frequency-dispersion in C-V characteristics and threshold voltage hysteresis are effectively suppressed, owing to improved interface quality. The new MOSC-HEMTs exhibit a maximum drain current of 660 mA/mm, a field-effect mobility of 165 cm2/V·s, a high on/off drain current ratio of ~1010, and low dynamic on-resistance degradation.

Interface Characterization of Normally-Off Al2O3/AlN/GaN MOS-Channel-HEMTs with an AlN Interfacial Layer

Recent Advances in GaN‐Based Power HEMT Devices

Ultra-thin-barrier (UTB) AlGaN/GaN heterostructure is utilized for fabrication of normally-OFF GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs). The sheet resistance of 2-D electron gas in the UTB Al0.22Ga0.78N(5-nm)/GaN heterostructure is effectively reduced by SiNx passivation grown by low-pressure chemical vapor deposition, from 2570 to $334~\Omega $ /□. The fabricated Al2O3/AlGaN/GaN MIS-HEMTs exhibit normally-OFF behavior with good $V_{\mathrm {TH}}$ uniformity and low $V_{\mathrm {TH}}$ -hysteresis. 20 mm-gate-width power devices featuring a low $R_{\sc {\mathrm{ on}}}$ of $0.75~\Omega $ ( $\text{I}_{\mathrm {D,MAX}} =6.5$ A) are also demonstrated on the platform.

High Uniformity Normally-OFF GaN MIS-HEMTs Fabricated on Ultra-Thin-Barrier AlGaN/GaN Heterostructure

In this letter, a plasma-free etch stop structure is developed for GaN HEMT toward enhancement-mode operation. The self-terminated precision gate recess is realized by inserting a thin AlN/GaN bilayer in the AlGaN barrier layer. The gate recess is stopped automatically at the GaN insertion layer after high-temperature oxidation and wet etch, leaving a thin AlGaN barrier to maintain a quantum well channel that is normally pinched off. With addition of an Al2O3 gate dielectric, quasi normally OFF GaN MOSHEMTs have been fabricated with high threshold uniformity and low ON-resistance comparable with the normally ON devices on the same wafer. A high channel mobility of 1400 cm $^{2}/\textrm {V}\cdot \textrm {s}$ was obtained due to the preservation of the high electron mobility in the quantum-well channel under the gate.

A GaN HEMT Structure Allowing Self-Terminated, Plasma-Free Etching for High-Uniformity, High-Mobility Enhancement-Mode Devices

Threshold voltage drift under gate bias stress was investigated in gate-recessed enhancement mode (E-mode) GaN MOSFET and depletion mode (D-mode) GaN MOS high-electron-mobility transistor (MOSHEMT) with Al2O3 gate dielectric layer. Besides the positive shift of threshold voltage in both devices under positive gate stress, it is also found that positive shift could also exist in E-mode GaN MOSFET under negative gate bias stress, while negative shift is observed in D-mode MOSHEMT. A three-step trapping and detrapping process was observed in the drain current transient of the device after negative gate bias stress. It was suggested that gate electron injection and the following trapping in the "damaged" gate recessed GaN channel layer is the dominant mechanism for the positive shift of the threshold voltage under negative gate bias in the enhancement mode GaN MOSFET.

https://iopscience.iop.org/article/10.7567/JJAP.54.044101/pdf

Investigation of the threshold voltage drift in enhancement mode GaN MOSFET under negative gate bias stress

The time-dependent threshold voltage drift induced by fast interface traps in a fully gate-recessed normally-off GaN MOSFET is studied. It is found that the degree and time scale of the shift in threshold voltage are consistent with the density and time constant of interface traps at the MOS interface. The device based on wet etching delivers higher interface quality and threshold voltage stability than that based on dry etching. Nitrogen deficiency and high oxygen coverage are considered to be the origins of the high interface trap density in the MOSFET fabricated by dry etching.

https://iopscience.iop.org/article/10.7567/APEX.9.091001/pdf

Time-dependent threshold voltage drift induced by interface traps in normally-off GaN MOSFET with different gate recess technique

The invention provides a device structure capable of improving the mobility of an enhanced GaN MOS channel and an implementation method, belongs to the technical field of microelectronics, and relates to manufacturing of a GaN-based power electronic device. The structure comprises a substrate, a GaN or AlN buffer layer, an InGaN layer, a GaN layer, an AlGaN layer, a mask dielectric layer, an insulated gate dielectric layer and a gate metal, wherein an AlGaN/GaN heterojunction material epitaxially grows on the substrate and a source and a drain are formed on the structure. channel electrons under a grid are far away from the interface of the insulated gate dielectric layer and a GaN channel layer by employing a polarization electric field between the InGaN layer and the GaN layer, interface scattering of the channel electrons is reduced, and the electron mobility and the maximum drain current density in the channel are improved. The thickness of an InGaN back barrier layer, an In component and the thickness of the GaN channel layer are simulated through a computer to obtain optimal values. By the device structure, the problem of electron mobility degradation of the channel can be effectively solved, the saturation current of the GaN-based enhanced device is increased and the electrical properties of an enhanced GaN MOS are greatly improved.

Fei Sang

Papers

A GaN HEMT Structure Allowing Self-Terminated, Plasma-Free Etching for High-Uniformity, High-Mobility Enhancement-Mode Devices

Investigation of the threshold voltage drift in enhancement mode GaN MOSFET under negative gate bias stress

Time-dependent threshold voltage drift induced by interface traps in normally-off GaN MOSFET with different gate recess technique

Device structure capable of improving mobility of enhanced GaN MOS channel and implementation method