Journal ArticleDOI
HERMES: an infrastructure for low area overhead packet-switching networks on chip
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TLDR
The state of the art in networks on chip is reviewed, an infrastructure called Hermes is described, targeted to implement packet-switching mesh and related interconnection architectures and topologies and the design validation of the Hermes switch is presented.About:
This article is published in Integration.The article was published on 2004-10-01. It has received 578 citations till now. The article focuses on the topics: Network on a chip & System on a chip.read more
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Journal ArticleDOI
A survey of research and practices of Network-on-chip
TL;DR: The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.
Book
On-Chip Communication Architectures: System on Chip Interconnect
Sudeep Pasricha,Nikil Dutt +1 more
TL;DR: This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design, and will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on- chip communication architectures.
Journal ArticleDOI
CoMPSoC: A template for composable and predictable multi-processor system on chips
TL;DR: A Composable and Predictable Multi-Processor System on Chip (CoMPSoC) platform template is proposed, which enables a divide-and-conquer design strategy, where all applications, potentially using different programming models and communication paradigms, are developed and verified independently of one another.
Proceedings ArticleDOI
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
Nachiket Kapre,Nikil Mehta,Michael deLorimier,Raphael Rubin,H. Barnor,Michael Wilson,Michael G. Wrighton,André DeHon +7 more
TL;DR: Modular and scalable networks which operate on a Xilinx XC2V6000-4 at 166MHz are demonstrated and time-multiplexed, offline scheduling offers up to a 63% performance increase over online, packet-switched scheduling for equivalent topologies.
Proceedings ArticleDOI
A Complete Network-On-Chip Emulation Framework
TL;DR: This paper presents a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort, and shows a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Networks on chips: a new SoC paradigm
Luca Benini,G. De Micheli +1 more
TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Proceedings ArticleDOI
Route packets, not wires: on-chip interconnection networks
William J. Dally,Brian Towles +1 more
TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Book
Interconnection Networks: An Engineering Approach
TL;DR: The book's engineering approach considers the issues that designers need to deal with and presents a broad set of practical solutions that address the challenges and details the basic underlying concepts of interconnection networks.