Fernando Silveira

TL;DR: A novel modular architecture for a step-down Switched-Capacitor Converter for Ultra Low Power applications and a technique for increasing efficiency by recycling the charge stored in parasitic capacitances is presented.

TL;DR: A high slew-rate OTA based on a non-linear current mirror which dramatically reduces the quiescent current is presented and the compactness of the proposed architecture does not require so much silicon area as other more complex adaptive bias architectures.

TL;DR: An integrated biopotential preamplifier architecture targeting applications that simultaneously require high common-mode rejection ratio (CMRR), low noise, high input common- mode range (ICMR), and current-efficiency (low Noise Efficiency Factor or NEF) is presented.

TL;DR: The main goal of this paper is to show that electronic hardware design is a valid alternative to be taken into account when deciding on the implementation of a certain development or the technical economical possibility of acertain product in this context.

TL;DR: As part of a Low-IF ZigBee receiver, a 2.4GHz differential common source low noise amplifier, implemented in a 90nm mixed/RF 7M CMOS process and designed in moderate inversion, is presented in this work.