Showing papers by "Franco Maloberti published in 2021"

A Hybrid Single-Inductor Bipolar-Output DC–DC Converter With Floating Negative Output for AMOLED Displays

Abstract: This article presents a hybrid single-inductor bipolar-output (SIBO) dc–dc converter for active-matrix organic light-emitting diode (AMOLED) displays, which are relatively more sensitive to the supply noise on the positive supply. First, to improve the display quality we adopt a floating negative output configuration to migrate all the switching ripples into the negative output, achieving a near-zero voltage ripple on the positive output. Second, we design low-power shunt regulators, which only deal with a small portion of the output ripple, to regulate the positive output voltage further, improving the load transient response. Besides, the hybrid topology and the proposed cross-coupled bootstrap-based level-shifter, with a dual-PMOS inverter buffer, only uses standard CMOS devices without deep-n-well, reducing the chip area and cost. The proposed converter, implemented in 0.35- $\mu \text{m}$ CMOS with 5-V devices, operates at 1 MHz, leading to a measured positive output voltage ripple lower than 1 mV (all conditions). It achieves a measured 3-mV undershoot voltage and, an unnoticeable overshoot voltage on the positive output, when the output current varies between 30 and 350 mA. The measured peak power efficiency is 89.3% at 1.1-W output power. The maximum output power is 3.5 W.

A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS

Abstract: This paper reports a reference-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring fast and robust frequency acquisition without identifying the frequency error polarity. The key idea is a deliberately-current-mismatch charge-pump pair, which avoids the need of a complex high-speed data path or clock path during frequency acquisition. Prototyped in 28nm CMOS, our BBCDR covers a 47.6-to-58.8Gb/s PAM-4 input automatically. The achieved energy efficiency (≤0.25pJ/bit) and acquisition speed $[9.8(\text{Gb}/\mathrm{s})/\mu\mathrm{s}]$ compare favorably with the prior art. Keywords—CMOS, reference less, single loop, half-rate, bang-bang clock and data recovery (BBCDR), frequency detector (FD), charge pump (CP), 4-level pulse amplitude modulation (PAM-4), zero (ZNC), positive (PNC), and negative (NNC) net current.

A Time-Interleaved 2 nd -Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation

Abstract: This article presents a $4\times $ time-interleaved (TI) 2nd-order discrete-time (DT) delta-sigma modulator (DSM). We propose a digital feed-forward extrapolation by first digitizing the internal analog nodes’ information from one channel, and then extrapolating the other channels in the digital domain. As a result, this DSM only needs two operational amplifiers (op-amps) to realize four interleaving paths, thus reducing analog hardware overheads. Meanwhile, we linearize the digital feed-forward paths through injected dithering. We present the derivation of extrapolating TI DSM starting from a single-channel DSM, while we also list and compare several conventional TI approaches. Implemented in 28-nm CMOS, this modulator achieves an equivalent output-sampling rate of 2.08 GS/s, $208\times $ oversampling ratio (OSR), and a signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 86.1 dB/98 dB with 5-MHz bandwidth (BW). The power consumption is 23.1 mW, which results in a Schreier Figure of Merit (FoM) of 169.5 dB.

A 2.4-GHz CMOS Differential Class-DE Rectifier With Coupled Inductors

Abstract: In this article, we present a 2.4-GHz differential class-DE synchronous rectifier. First, we investigate zero-voltage switching (ZVS), zero-current switching (ZCS), and impedance matching requirements for the single-ended class-DE rectifier. Then, we propose a differential topology that achieves near-optimum ZVS, ZCS, and impedance matching with a reduced number of LC networks. We use a coupled inductor structure to reduce the cost overhead of the differential topology and discuss its design considerations. To maintain the ZVS/ZCS operation within a wide input power range, we employ an adaptive bias circuit to adjust the gate bias voltages with the input power. Additionally, we discuss the imperfections caused by load variation. The chip, fabricated in a 65-nm CMOS process, measures the peak power conversion efficiency (PCE) of 68.5% at a 9-dBm input power with a 250-Ω load resistance. The measured input power range when PCE > 40% is 16 dB.