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Design Of Analog Cmos Integrated Circuits

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alternate comparators clocked asynchronously and a redundant capacitive DAC with constant common mode to improve the accuracy of the comparator. A low-power, clocked capacitive reference buffer is used, and fractional reference voltages are provided to reduce the number of unit capacitors in the capacitive DAC (CDAC). The ADC stacks the CDAC with the reference capacitor to reduce the area and enhance the settling speed. Background calibration of comparator offset is implemented. The ADC consumes 3.1 mW from a 1 V supply and occupies 0.0015 mm2.

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

A time-interleaved multichannel analog-to-digital converter (ADC) achieves high sampling rates with the drawback of additional distortions caused by channel mismatches. In this paper, we consider the dependency of the signal-to-noise-and-distortion ratio (SINAD) on the combination of several different channel mismatch effects. By using either explicitly given mismatch parameters or given parameter distributions, we derive closed-form equations for calculating the explicit or the expected SINAD for an arbitrary number of channels. Furthermore, we extend the explicit SINAD by the impact of timing jitter. We clarify how channel mismatches interact and perform a worst case analysis of the explicit SINAD for individual mismatch errors. We also show that equations describing the expected SINAD of individual mismatch errors are special cases of our general formulation. We indicate how to use the expected SINAD for finding efficient optimization priorities and demonstrate the importance of worst case analyses.

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The impact of combined channel mismatch effects in time-interleaved ADCs

The digital low dropout regulator (D-LDO) has drawn significant attention recently for its low-voltage operation and process scalability. However, the tradeoff between current efficiency and transient response speed has limited its applications. In this brief, a coarse–fine-tuning technique with burst-mode operation is proposed to the D-LDO. Once the voltage undershoot/overshoot is detected, the coarse tuning quickly finds out the coarse control word in which the load current should be located, with large power MOS strength and high sampling frequency for a fixed time. Then, the fine-tuning, with reduced power MOS strength and sampling frequency, regulates the D-LDO to the desired output voltage and takes over the steady-state operation for high accuracy and current efficiency. The proposed D-LDO is verified in a 65-nm CMOS process with a 0.01-mm2 active area. The measured voltage undershoot and overshoot are 55 and 47 mV, respectively, with load steps of 2 to 100 mA with a 20-ns edge time. The quiescent current is 82 $\mu\textrm{A}$ , with a 0.43-ps figure of merit achieved. Moreover, the reference tracking speed is 1.5 $\textrm{V}/\mu\textrm{s}$ .

A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation

This brief presents a dual-path CMOS rectifier with adaptive control for ultrahigh-frequency (UHF) RF energy harvesters. The input power range with high power conversion efficiency (high PCE) of the rectifier is extended by the proposed architecture, which includes a low-power path and a high-power path. The dual-path rectifier with an adaptive control circuit is fabricated in a 65-nm CMOS process. Operating at 900 MHz and driving a 147-kΩ load resistor, the measured PCE of this work can be maintained above 20% with an 11-dB input range from -16 to -5 dBm, while only an 8-dB input range can be achieved with traditional single-path rectifiers. A sensitivity of -17.7 dBm is measured with 1-V output voltage across a capacitive load.

A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting

An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integrated circuit implementation, the proposed SAR ADC achieves rapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input. The measured FOM is 73 fJ/conversion-step at 400 MS/s from 1.2-V supply and 42 fJ/conversion-step at 250 MS/s from a 1-V supply. The active area with the digital calibration is 0.028 mm2.

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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). The proposed comparator reduces the input referred noise by half and shows a better output driving capability when compared with the previous work. The offset, noise and power consumption can be controlled by a clock delay which allows simple reconfiguration. Moreover, the proposed offset calibration technique improves the offset voltage from 11.6mV to 533μV at 1 sigma. A prototype of the comparator is implemented in 90nm 1P8M CMOS with experimental results showing 320μV input referred noise at 1.5GHz with 1.2V supply.

Sai-Weng Sin

Papers

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation

A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS