http://ieeexplore.ieee.org/iel5/5610941/5624686/05624745.pdf

Power electronics

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

CMOS image sensors: electronic camera-on-a-chip

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

A novel method for the active compensation of parasitic capacitances in high speed resistor string D/A converters is described. The experimental results obtained from a 10 bit DAC show that the approach proposed is essential to the achievement of a 50 MHz clock rate when using commercial 1.2 /spl mu/m CMOS analog technology. >

Active compensation of parasitic capacitances in a 10 bit 50 MHz CMOS D/A converter

A circuit is described which uses one oversampling frequency synthesizer in an interleaved mode to generate dual-tone multifrequency (DTMF) telephone dialing tones. The synthesizer is based on direct digital synthesis using phase accumulation. The digital-to-analog conversion is carried out using a first-order sigma-delta converter. This sigma-delta converter requires only a simple second-order RC filter, eliminating the need for a switched capacitor filter. Measurements on the circuit confirm that all specifications of the DTMF are fulfilled. >

An oversampling-based DTMF generator

An apparatus for generating a digital signal representative of an analog signal includes two signal conversion devices, each having an analog signal section coupled with an input locus and a digital signal section coupled between the analog signal section and an output locus. The signal conversion devices receive sampled analog signals that are phase-offset by a first phase difference. Two feedback devices are each coupled between the output locus of one signal conversion device and the analog signal section of the other signal conversion device to convey feedback signals that are phase-offset by a second phase difference. The first phase difference and the second phase difference cooperate to affect power density spectrum of a resultant digital output signal at at least one predetermined frequency. The resultant digital output signal is a summing of a digital output signals presented by the two signal conversion devices at their output loci.

Apparatus for generating at least one digital output signal representative of an analog signal

The design of low-power rail-to-rail output buffers for high capacitive loads is critical. In particular, control of the output current, constant input transconductance and output stage driving must be well confined. In this paper we discuss the major design constraints and present a new topology for a CMOS rail-to-rail output buffer. The experimental results show that the proposed architecture is suitable for input-output signals within the full dynamic.

Novel circuit solutions for rail-to-rail CMOS buffer

The automatic control of the matching impedance in chip-to-chip interconnections is described. The proposed method is based on an optimization algorithm that uses the sign of error and the sign of the coupling branch current. A possible implementation of the system is described and computer simulations at the behavioral level are presented.

/pdf/automatic-impedance-control-for-chip-to-chip-49yezkwu3k.pdf

Franco Maloberti

Papers

Active compensation of parasitic capacitances in a 10 bit 50 MHz CMOS D/A converter

An oversampling-based DTMF generator

Apparatus for generating at least one digital output signal representative of an analog signal

Novel circuit solutions for rail-to-rail CMOS buffer

Automatic impedance control for chip-to-chip interconnections