http://ieeexplore.ieee.org/iel5/5610941/5624686/05624745.pdf

Power electronics

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

CMOS image sensors: electronic camera-on-a-chip

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

A low-voltage, low-power mixer operating at a supply voltage of 0.9 V while consuming 4.7 mW is presented. The circuit achieves the multiplication using current mode processing. Moreover, non-conventional differential pairs that do not require current tail generators are utilized. The circuit has been fabricated in a standard double-poly, triple-metal 0.35 /spl mu/m CMOS process having a threshold voltage of 0.6 V. Measurement results for 900 MHz and 800 MHz input signals indicate that the circuit has an IIP3 of 3.5 dBm, a 1 dB compression point of -8 dBm and a noise figure of 13.5 dB.

/pdf/a-900-mhz-0-9-v-low-power-cmos-downconversion-mixer-4vvmk4acj6.pdf

A 900 MHz, 0.9 V low-power CMOS downconversion mixer

The goal of this paper is to present an extension of previously presented behavioral models, implemented in the Matlab/Simulink/spl trade/ environment. This toolbox allows us to simulate at behavioral level most of the switched-capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulator non-idealities, such as sampling jitter, kT/C noise and operational amplifier limitations (finite bandwidth, finite DC gain, slow rate and saturation). Although very effective in simulating wide-band, medium-resolution /spl Sigma//spl Delta/ converters the lack of a model for flicker noise and multi-bit quantizers makes this toolbox less attractive for simulating narrow band high resolution converters. The proposed extension not only fixes this limitation, but introduces a predictive model of the effect of capacitor mismatch in the internal multi-bit D/A converter.

/pdf/improved-modeling-of-sigma-delta-modulator-non-idealities-in-1uf8yka2bo.pdf

Improved modeling of sigma-delta modulator non-idealities in Simulink

This paper describes a 0.35- m CMOS fourth-order bandpass analog-digital sigma-delta ( ) modulator for wide- band base stations receivers. The modulator, based on a time-in- terleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dy- namic range of 72 dB (12 bits of resolution) with a signal band- width of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capa- bilities, and occupies 20 mm of silicon area.

A Wide-Band 280-MHz Four-Path Time-Interleaved

A system for wireless power transfer and data communication of implantable bio-monitoring systems is presented. The proposed solution uses a servo-controlled power transmitter moved under the animal moving space. An $x$ - $y$ movable magnetic coil transmits the required power with a level able to keep constant the received energy by the bio-sensor system. The power is transferred via the optimized remote powering link at 13.56 MHz. The received ac signal is converted to dc voltage with a passive full-wave integrated rectifier and the voltage regulator supplies 1.8 V for the implantable sensor system. The sensor control and readout circuit measures the current on the bio-sensors and transmit the data to the transmitter. The sensor data are transmitted to an external reader by a low-power OOK transmitter and received by a custom designed receiver at 869 MHz. The results are shown in a tablet computer in real time continuously. The long-term characterization of the implantable system is verified by a fully bio-compatible packaged implant with 30 days measurement. A complete prototype is also presented to prove the overall system performance with the experimental in vitro measurement.

/pdf/a-system-for-wireless-power-transfer-and-data-communication-50efofuzy5.pdf

A System for Wireless Power Transfer and Data Communication of Long-Term Bio-Monitoring

Deisgn automation for analog/mixed-signal (A/MS) circuits and systems is still lagging behind compared to what has been reached in the digital area.As System-on-Chip (SoC) designs include analog components in more cases, these analog parts become even more a bottle neck in the overall design process.The paper is dedicated to latest R&D activities within the MEDEA+ project ANASTASIA+.Main focus will be the development of seamless top-down design methods for integrated analog and misx-signal systems and to achieve a high level of automation and reuse in the A/MS design process.These efforts are motivated by the urgent need to close the current gap in the industrial design flow between system specification and design on the one hand and block-level circuit design on the other hand.The paper will focus on the three subtopics starting with the top-down design flow with applications from circuits sizing, design centering, and automated behaviorial modeling.The next part focuses on modeling and simulation of specific functionalities in sigma-delta design while the last section is dedicated to a mixed-signal System-on-Chip design environment.

/pdf/from-system-specification-to-layout-seamless-top-down-design-354l6wa922.pdf

Franco Maloberti

Papers

A 900 MHz, 0.9 V low-power CMOS downconversion mixer

Improved modeling of sigma-delta modulator non-idealities in Simulink

A Wide-Band 280-MHz Four-Path Time-Interleaved

A System for Wireless Power Transfer and Data Communication of Long-Term Bio-Monitoring

From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications