http://ieeexplore.ieee.org/iel5/5610941/5624686/05624745.pdf

Power electronics

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

CMOS image sensors: electronic camera-on-a-chip

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

An integrated circuit for a GSM system is described which acts as a raised cosine shaper for the ramp up and ramp down of a transmitted burst. By use of this shaper, GSM specifications for switching transient spectrum and power level versus time are fully met. The circuit which includes two 8 bit D/A converters, was fabricated using a 2 ?m CMOS process and its size is about 3*2.8 mm2.

http://ieeexplore.ieee.org/iel5/5468555/5468556/05469290.pdf

Raised Cosine Waveform Shaper for GSM Base Station

The embodiment of the utility model relates to an electronic converter and an integrated circuit. The converter includes a first switch coupled between a first input terminal and a first terminal of the inductor, and a second switch coupled between a second terminal of the inductor and a second input terminal. A third switch is coupled between the second terminal of the inductor and the first output terminal, and a fourth switch is coupled between the first terminal of the inductor and the second output terminal. A capacitor is coupled between the first output terminal and the second output terminal. The control circuit monitors the regulated voltage between the first output terminal and the second output terminal. During the charging phase, the first switch and the second switch are closed to charge the inductor. During the discharge phase, the third switch and the fourth switch are closed to charge the capacitor and increase the regulated voltage. The control circuit adjusts the duration of the charging phase and/or the discharging phase to adjust the adjusted voltage.

Electronic converter and integrated circuit

This paper presents a 500 kBit/s modem for space applications, designed for interfacing the satellite equipment with the On-Board Data Handling (OBDH) bus system. The 28 mm2chip, fabricated in a 0.8 µm SOI radiation-hard CMOS process, achieves a bit-error rate as low as 10-14with 120 mV RMS of noise consuming 64 mW from a 5 V power supply.

/pdf/a-0-8-um-soi-cmos-on-board-data-handling-bus-modem-for-3tzeclgyi4.pdf

A 0.8 &#181;m SOI CMOS on-board data handling bus modem for satellite applications

This paper gives an overview on the key features of the several building blocks constituting modern nomadic systems. Different micro-power energy harvesting techniques are described and discussed. In addition, this paper reviews the state of the art and provides recently published examples of low power low voltage analog circuits, such as operational amplifiers, reference generators, and data converters.

Very-low-voltage and ultra-low-power analog circuits for nomadic applications

A novel technique for achieving noise shaping in oversampled converters is proposed. It uses the adaptive algorithm to minimize the mean square quantization error. The circuit implementation looks like a sigma-delta modulator and requires limited additional circuits for the necessary multipliers. Simulation results, confirmed by experimental measurements, show that more than 15dB in the SNR are gained with respect to an equivalent sigma-delta counterpart in the low signal level range.

/pdf/adaptive-noise-shaping-adc-based-on-lms-algorithm-31qtjvnw8p.pdf

Franco Maloberti

Papers

Raised Cosine Waveform Shaper for GSM Base Station

Electronic converter and integrated circuit

A 0.8 µm SOI CMOS on-board data handling bus modem for satellite applications

Very-low-voltage and ultra-low-power analog circuits for nomadic applications

Adaptive noise shaping ADC based on LMS algorithm

Franco Maloberti

Papers

Raised Cosine Waveform Shaper for GSM Base Station

Electronic converter and integrated circuit

A 0.8 &#181;m SOI CMOS on-board data handling bus modem for satellite applications

Very-low-voltage and ultra-low-power analog circuits for nomadic applications

Adaptive noise shaping ADC based on LMS algorithm

A 0.8 µm SOI CMOS on-board data handling bus modem for satellite applications