http://ieeexplore.ieee.org/iel5/5610941/5624686/05624745.pdf

Power electronics

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

CMOS image sensors: electronic camera-on-a-chip

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

This paper presents a 5-bit 1.25-GS/s folding flash ADC. The prototype achieves a folding factor of four with a capacitive folding technique that only consumes dynamic power. Incorporated with various calibration schemes, folding errors and the comparator's threshold inaccuracies are corrected, thus allowing a low input capacitance of 80 fF. The design is fabricated using 65-nm digital CMOS technology and occupies 0.007 mm 2. The maximum DNL and INL post calibration are 0.67 and 0.47 LSB, respectively. Measurement results show that the ADC can achieve 1.25 GS/s at 1-V supply with a total power consumption of 595 μW. In addition, it exhibits a mean ENOB of 4.8b at dc among ten chips, which yields an FoM of 17 fJ/conversion-step.

A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS

An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and sub-threshold operation enables the use of a power-effective, singlestage op-amp with 69dB-gain. The ADC achieves peak SNDR of 57.6dB while consuming 2.1mW from 1-V analog and 0.85-V digital supply, resulting in an FoM of 57fJ/step.

/pdf/an-11b-60ms-s-2-1mw-two-step-time-interleaved-sar-adc-with-1d4f7gyagv.pdf

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H

This paper presents a four-folded current-mode vertical Hall device. The current spinning technique is applied to a vertical Hall sensor driven in current mode to eliminate the o set and to increase the sensitivity. Di erent geometries have been studied and simulated by using a simulator based on finite element method. A four-folded three contacts vertical Hall device model displayed the lowest residual o set and the best sensitivity. Simulations results, obtained in two di erent environments, are compared and discussed. COMSOL results are validated with respect to the electrical behavior of an 8-resistor Verilog-A model implemented in Cadence environment. Simulations show that the achieved sensitivity can be better than 160 mT 1 , a remarkable performance for vertical Hall sensors.

/pdf/analysis-and-modeling-of-four-folded-vertical-hall-devices-5kc42hdxk0.pdf

Analysis and modeling of four-folded vertical Hall devices in current domain

In this paper, a novel 10-bit A/D converter based on a pipeline-like architecture specific for low-noise, self-triggered sensors, (e.g., X-rays and 7-rays spectrometry) is presented. The main innovative feature of the proposed A/D structure is the concept that, for a sampled input signal, a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal (clock). The conversion is obtained asynchronously propagating the partial conversions and the residues through the various stages. This concept is validated by means of a prototype ADC fabricated in a standard 0.35 mum CMOS technology. The active area is 2.24 mm2, and it provides a conversion in 2.5 mus (i.e., it can operate with a 400 kS/s data rate) featuring an ENOB equal to 8.91.

/pdf/a-clock-less-10-bit-pipeline-like-a-d-converter-for-self-1dwnenoo3i.pdf

A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors

This integrated single inductor dual-output boost DC/DC converter provides two independently regulated outputs with maximum efficiency at 83%. The converter operates in PWM and discontinuous mode at 500kHz using a 6.8uH inductor. Each output is time-multiplexed and regulated via current mode control. A drain-extended 0.13um technology allows backlight application up to 11V operation. The chip occupies 1.56 mm.

Franco Maloberti

Papers

A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H

Analysis and modeling of four-folded vertical Hall devices in current domain

A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors

A PWM dual-output DC/DC boost converter in a 0.13/spl mu/m CMOS technology for cellularphone backlight application