http://ieeexplore.ieee.org/iel5/5610941/5624686/05624745.pdf

Power electronics

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

CMOS image sensors: electronic camera-on-a-chip

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

This paper presents a level-shifting technique for high-voltage power converter applications. The proposed circuit effectively combines capacitive and active coupling of the input low (high) side signal to the output high (low) side to reduce the propagation delay of the level-shifting operation. By using the resulting circuit, (i) the high-side PMOS switch is driven at high speed and (ii) a quasi-zero voltage switching (ZVS) of the low side NMOS switch is achieved. The circuit has been designed and simulated at the transistor level using a 0.18-μm BCD process. At the high-side, remarkable simulated average level-shifter propagation delay and total driving delay have been achieved: 0.5 ns and 1.9 ns, respectively. The proposed level-shifter consumes 48.5 μA of average current.

A high-speed level shifting technique and its application in high-voltage, synchronous DC-DC converters with quasi-ZVS

High-order high-frequency bandpass sigma-delta modulators are becoming the standard front-end for radio-frequency systems. They allow direct digital demodulation of intermediate frequency signals, thus avoiding tuning of analog demodulators. This paper presents a suitable solution for the design of a fourth-order bandpass sigma-delta modulator. The designed modulator has been implemented in a 1.2-?m BiCMOS technology and gives 9 bits of resolution for a 42.8 MHz sampling rate over a signal band of 200 kHz.

https://ieeexplore.ieee.org/iel5/5468575/5468576/05468630.pdf

A 10.7-MHz N-Path Fourth-Order Bandpass Sigma-Delta Modulator

Conventional binary-weighted and oversampling techniques are very popular methods of performing D/A conversions. However, the accuracy required in the component matching limits the resolution obtainable with a binary-weighted converter to approximately 8 bits, unless very sophisticated techniques (including selfcalibration) are used. Moreover, the resolution which can be achieved with an oversampled converter is limited by the oversampling factor actually obtainable for a predetermined signal bandwidth with any given integration technology. This paper presents a novel combined conversion approach, which takes advantage of the positive features of both the above techniques. The most significant bits (MSBs) are converted with the binary-weighted technique, while the least significant bits (LSBs) are converted with the oversampling technique.

https://ieeexplore.ieee.org/iel3/1206/3984/00151987.pdf

Multibit oversampled DAC with dynamic matching of current sources

This paper presents a current-mode 64×1 early vision chip, including integrated photodiodes and a programmable "perceptual engine", which can implement various perceptual algorithms, such as Gabor filters. The proposed chip can be used for early vision tasks as edge detection, texture analysis, depth estimation and motion analysis. The perceptual engine exploits the properties of MOS transistors to achieve widely programmable coefficients for the distributed lattice network which implements the perceptual operators. The 8.9 × 1.8 mm2chip, fabricated in a conventional 0.8 µm CMOS process, consumes 56 mW from a 5 V supply.

/pdf/a-current-mode-64-1-programmable-gabor-filter-for-early-3l7o1i2stm.pdf

A current-mode 64&#215;1 programmable gabor filter for early vision systems

The low-frequency noise in SC ladder filters can be reduced by using a time-sharing technique. An example of a single-op-amp, second-order lowpass filter illustrates the design approach to obtaining a total noise suppression at frequencies near to zero.

Franco Maloberti

Papers

A high-speed level shifting technique and its application in high-voltage, synchronous DC-DC converters with quasi-ZVS

A 10.7-MHz N-Path Fourth-Order Bandpass Sigma-Delta Modulator

Multibit oversampled DAC with dynamic matching of current sources

A current-mode 64×1 programmable gabor filter for early vision systems

Low-frequency noise reduction in SC ladder filters

Franco Maloberti

Papers

A high-speed level shifting technique and its application in high-voltage, synchronous DC-DC converters with quasi-ZVS

A 10.7-MHz N-Path Fourth-Order Bandpass Sigma-Delta Modulator

Multibit oversampled DAC with dynamic matching of current sources

A current-mode 64&#215;1 programmable gabor filter for early vision systems

Low-frequency noise reduction in SC ladder filters

A current-mode 64×1 programmable gabor filter for early vision systems