Emerging challenges and materials for thermal management of electronics

Power has become the primary design constraint for chip designers today. While Moore's law continues to provide additional transistors, power budgets have begun to prohibit those devices from actually being used. To reduce energy consumption, voltage scaling techniques have proved a popular technique with subthreshold design representing the endpoint of voltage scaling. Although it is extremely energy efficient, subthreshold design has been relegated to niche markets due to its major performance penalties. This paper defines and explores near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region retains much of the energy savings of subthreshold operation with more favorable performance and variability characteristics. This makes it applicable to a broad range of power-constrained computing segments from sensors to high performance servers. This paper explores the barriers to the widespread adoption of NTC and describes current work aimed at overcoming these obstacles.

Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits

Power has become the primary design constraint for chip designers today. While Moore's law continues to provide additional transistors, power budgets have begun to prohibit those devices from actually being used. To reduce energy consumption, voltage scaling techniques have proved a popular technique with subthreshold design representing the endpoint of voltage scaling. Although it is extremely energy efficient, subthreshold design has been relegated to niche markets due to its major performance penalties. This paper defines and explores near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region retains much of the energy savings of subthreshold operation with more favor- able performance and variability characteristics. This makes it applicable to a broad range of power-constrained computing segments from sensors to high performance servers. This paper explores the barriers to the widespread adoption of NTC and describes current work aimed at overcoming these obstacles.

Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits Future computer systems promise to achieve an energy reduction of 100 or more times with memory design, device structure, device fabrication techniques, and clocking, all optimized for low-voltage operation.

Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. TSV resistance, inductance, and capacitance need to be modeled to determine their impact on the performance of a 3-D circuit. In this paper, the RLC parameters of the TSV are modeled as a function of physical parameters and material characteristics. Models are validated with the numerical simulators like Raphael and Sdevice and with experimental measurements. The TSV RLC model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures. Finally, this paper also proposes a simplified lumped TSV model that can be used to simulate 3-D circuits.

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Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 108 vias/cm2), and extremely aggressive wafer-to-wafer alignment (submicron) capability.

G. U. Singco

Papers

Three-dimensional integrated circuits