D.C. La Tulipe

TL;DR: The process steps and design aspects that were developed at IBM to enable the formation of stacked device layers are reviewed, including the descriptions of a glass substrate process to enable through-wafer alignment and a single-damascene patterning and metallization method for the creation of high-aspect-ratio capability.

TL;DR: An overview of wafer-level three-dimensional integration technology is provided, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits.

TL;DR: In this paper, the authors present solutions to the key process technology challenges of 3D integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment.

TL;DR: Measurements of a current-to-current coupling between 2D and 3D electron-gas layers in the AlGaAs/GaAs system are reported, for the first time, utilizing an GaAs gate as the 3DEG layer.

TL;DR: In this article, the performance of self-aligned HfO/sub 2/based nMOSFETs with various metal gate electrodes (W, TaN, TiN, and TaSiN) is optimized.