Steven E. Steen

TL;DR: The process steps and design aspects that were developed at IBM to enable the formation of stacked device layers are reviewed, including the descriptions of a glass substrate process to enable through-wafer alignment and a single-damascene patterning and metallization method for the creation of high-aspect-ratio capability.

TL;DR: In this article, germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer are presented.

TL;DR: In this paper, the authors present solutions to the key process technology challenges of 3D integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment.

TL;DR: In this paper, the authors report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer.

TL;DR: In this paper, the hybrid orientation technology (HOT) has been used for the first time in a ring oscillator with L/sub poly/ about 85nm and t/sub ox/=2.2nm, resulting in 21% improvement compared with control CMOS on (100) orientations.