G
Geert Van der Plas
Researcher at Katholieke Universiteit Leuven
Publications - 112
Citations - 1168
Geert Van der Plas is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: CMOS & Comparator. The author has an hindex of 17, co-authored 112 publications receiving 1015 citations. Previous affiliations of Geert Van der Plas include IMEC.
Papers
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Journal ArticleDOI
A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS
TL;DR: A fully flexible continuous-time CT Δ Σ with programmable bandwidth, resolution and power consumption in 1.2 V 90 nm CMOS is presented able to satisfy A/D converters with high dynamic range and large bandwidth at the lowest possible power consumption.
Proceedings ArticleDOI
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS
TL;DR: A four-way interleaved converter, of which one channel is shown in Fig. 16.3.1, is presented, for communication in the unlicensed frequency band around 60GHz with very fast ADC with low resolution.
Journal ArticleDOI
Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS
Lynn Bos,Gerd Vandersteen,Pieter Rombouts,Arnd Geis,Alonso Morgado,Yves Rolain,Geert Van der Plas,Julien Ryckaert +7 more
TL;DR: It is shown that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35% and enables the power efficient implementation of multiple communication standards.
Journal ArticleDOI
A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS
TL;DR: A 2.2 GS/s 4×-interleaved 6b ADC in 40 nm digital CMOS is presented, which leverages threshold calibration to correct for amplifier and comparator imperfections, which allows the use of inherently nonlinear dynamic amplifiers.
Proceedings ArticleDOI
A 2.8-to-8.5mW GSM/bluetooth/UMTS/DVB-H/WLAN fully reconfigurable CTΔΣ with 200kHz to 20MHz BW for 4G radios in 90nm digital CMOS
TL;DR: A 0.4mm2 low-power fully-reconfigurable continuous-time (CT) feedforward ΔΣ ADC for 4G radios is implemented in 90nm CMOS by reconfiguring the topology architecture, quantizer bits, biasing current and component parameters, optimal power consumption can be achieved for every mode.