Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Silicon has long been the optimal material for electronics, but it is only relatively recently that it has been considered as a material option for photonics1. One of the key limitations for using silicon as a photonic material has been the relatively low speed of silicon optical modulators compared to those fabricated from III–V semiconductor compounds2,3,4,5,6 and/or electro-optic materials such as lithium niobate7,8,9. To date, the fastest silicon-waveguide-based optical modulator that has been demonstrated experimentally has a modulation frequency of only ∼20 MHz (refs 10, 11), although it has been predicted theoretically that a ∼1-GHz modulation frequency might be achievable in some device structures12,13. Here we describe an approach based on a metal–oxide–semiconductor (MOS) capacitor structure embedded in a silicon waveguide that can produce high-speed optical phase modulation: we demonstrate an all-silicon optical modulator with a modulation bandwidth exceeding 1 GHz. As this technology is compatible with conventional complementary MOS (CMOS) processing, monolithic integration of the silicon modulator with advanced electronics on a single silicon substrate becomes possible.

A high-speed silicon optical modulator based on a metal–oxide–semiconductor capacitor

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described. One optimized for highest speed and the other trading off speed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 /spl mu/m channel length at 2.5 V down to sub-0.1 /spl mu/m at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the power supply voltage will lead to a substantial rise in standby power compared to active power and some tradeoffs of performance and/or changes in design methods must be made. Key technology elements and their impact on scaling are discussed. It is shown that a speed improvement of about 7/spl times/ and over two orders of magnitude improvement in power-delay product (mW/MIPS) are expected by scaling of bulk CMOS down to the sub-0.1 /spl mu/m regime as compared with today's high performance 0.6 /spl mu/m devices at 5 V. However, the power density rises by a factor of 4/spl times/ for the high-speed scenario. The status of the silicon-on-insulator (SOI) approach to scaled CMOS is also reviewed, showing the potential for about 3/spl times/ savings in power compared to the bulk case at the same speed. >

CMOS scaling for high performance and low power-the next ten years

Silicon-on-insulator (SOI) CMOS offers a 20–35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-µm generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-µm generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-µm generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

SOI technology for the GHz era

A shift-and-ratio method for extracting MOSFET channel length is presented. In this method, channel mobility can be any function of gate voltage, and high source-drain resistance does not affect extraction results. It is shown to yield more accurate and consistent channel lengths for deep-submicrometer CMOS devices at room and low temperatures. It is also found that, for both nFET and pFET, the source-drain resistance is essentially independent of temperature from 300 to 77 K. >

A new 'shift and ratio' method for MOSFET channel-length extraction

A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.

Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys

A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

Ghavam G. Shahidi

Papers

CMOS scaling for high performance and low power-the next ten years

SOI technology for the GHz era

A new 'shift and ratio' method for MOSFET channel-length extraction

Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys

Patterned SOI regions on semiconductor chips