Showing papers in "Ibm Journal of Research and Development in 2002"

POWER4 system microarchitecture

Abstract: The IBM POWER4 is a new microprocessor organized in a system structure that includes new technology to form systems. The name POWER4 as used in this context refers not only to a chip, but also to the structure used to interconnect chips to form systems. In this paper we describe the processor microarchitecture as well as the interconnection architecture employed to form systems up to a 32-way symmetric multiprocessor.

Beyond the conventional transistor

Abstract: This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

CMOS design near the limit of scaling

Abstract: Beginning with a brief review of CMOS scaling trends from 1 µm to 01 µm, this paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length Both the standby power and the active power of a processor chip will increase precipitously below the 01-µm or 100-nm technology generation To extend CMOS scaling to the shortest channel length possible while still gaining significant performance benefit, an optimized, vertically and laterally nonuniform doping design (superhalo) is presented It is projected that room-temperature CMOS will be scaled to 20-nm channel length with the superhalo profile Low-temperature CMOS allows additional design space to further extend CMOS scaling to near 10 nm

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

Abstract: Significant challenges face DRAM scaling toward and beyond the 0.10-µm generation. Scaling techniques used in earlier generations for the array-access transistor and the storage capacitor are encountering limitations which necessitate major innovation in electrical operating mode, structure, and processing. Although a variety of options exist for advancing the technology, such as low-voltage operation, vertical MOSFETs, and novel capacitor structures, uncertainties exist about which way to proceed. This paper discusses the interrelationships among the DRAM scaling requirements and their possible solutions. The emphasis is on trench-capacitor DRAM technology.

Maintaining the benefits of CMOS scaling when scaling bogs down

Abstract: A survey of industry trends from the last two decades of scaling for CMOS logic is examined in an attempt to extrapolate practical directions for CMOS technology as lithography progresses toward the point at which CMOS is limited by the size of the silicon atom itself. Some possible directions for various specialized applications in CMOS logic are explored, and it is further conjectured that double-gate MOSFETs will prove to be the dominant device architecture for this last era of CMOS scaling.

SOI technology for the GHz era

Abstract: Silicon-on-insulator (SOI) CMOS offers a 20–35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-µm generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-µm generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-µm generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

Power-constrained CMOS scaling limits

Abstract: The scaling of CMOS technology has progressed rapidly for three decades, but may soon come to an end because of power-dissipation constraints. The primary problem is static power dissipation, which is caused by leakage currents arising from quantum tunneling and thermal excitations. The details of these effects, along with other scaling issues, are discussed in the context of their dependence on application. On the basis of these considerations, the limits of CMOS scaling are estimated for various application scenarios.

Reliability limits for the gate insulator in CMOS technology

Abstract: Aggressive scaling of the thickness of the gate insulator in CMOS transistors has caused the quality and reliability of ultrathin dielectrics to assume greater importance. This paper reviews the physics and statistics of dielectric wearout and breakdown in ultrathin SiO2-based gate dielectrics. Estimating reliability requires an extrapolation from the measeurment conditions (e.g., higher voltage) to normal operation conditions. To reduce the error in this extrapolation, long-term (>1 year) stress experiments have been used to measure the wearout and breakdown of ultrathin (<2 nm) dielectric films as close as possible to operating conditions. Measured over a sufficiently wide range of stress conditions, the time to breakdown (TBD) does not obey any simple "law" such as exponential dependence on electric field or voltage, as has been commonly assumed in reliability extrapolations. Thus, the interpretation of TBD data remains somewhat controversial. Present research is aimed at better understanding the nature of the electrical conduction through a breakdown spot, and the effect of the oxide breakdown on device and circuit performance. In some cases an oxide breakdown may not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

Interconnect opportunities for gigascale integration

Abstract: Throughout the past four decades, semiconductor technology has advanced at exponential rates in both productivity and performance. In recent years, multilevel interconnect networks have become the primary limit on the productivity, performance, energy dissipation, and signal integrity of gigascale integration. Consequently, a broad spectrum of novel solutions to the multifaceted interconnect problem must be explored. Here we review recent salient results of this exploration. Based upon prediction of the complete stochastic signal interconnect length distribution of a megacell, optimal reverse scaling of each pair of wiring levels provides a prime opportunity to minimize cell area, clock period, power dissipation, or number of wiring levels. Using a heterogeneous version of Rent's rule, a design methodology for the global signal, clock, and power/ground distribution networks for a system-on-a-chip has been derived. Wiring area, bandwidth, and signal integrity are the prime constraints on the design of the networks. Three-dimensional integration offers the opportunity to reduce the length of the longest global interconnects in a distribution by as much as 75%. Wafer-level batch fabrication of chip input/output interconnects and chip scale packages provides new benefits such as I/O bandwidth enhancement, simultaneous switching-noise reduction, and lower cost of packaging and testing. Microphotonic interconnects have long-term potential to reduce latency, power dissipation, and crosstalk while increasing bandwidth.

High-end server low-temperature cooling

Abstract: The IBM S/390® G4 CMOS system, first shipped in 1997, was the first high-end system to use refrigeration. The decision to employ refrigeration cooling instead of other cooling options such as high-flow air cooling or various water-cooling schemes focused on the potential system performance improvement obtainable by lowering coolant temperatures using a refrigeration system. This paper reviews the historical background of refrigeration from its use in the early 1800s to its implementation in computer systems in the early 1990s. The advantages and disadvantages of using refrigeration in the cooling of computer systems are examined. The advantages have outweighed the disadvantages, leading to the first use by IBM of refrigeration in cooling the S/390 G4 server. The design of the refrigeration system for the S/390 G4 system is described in detail, and some of the key parametric studies that contributed to the final design are described.

The circuit and physical design of the POWER4 microprocessor

Abstract: The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.

CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics

Abstract: The limitations of reliability of silicon dioxide dielectric for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is interpreted. Experimental data over a wide range of oxide thickness (TOX), voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. This work resolves seemingly contradictory observations regarding the temperature dependence of oxide breakdown. On the basis of these results, a unified, global picture of oxide breakdown is constructed, and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon-dioxide-based materials can provide a reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50-nm-technology node using silicon-dioxide-based gate insulators.

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems

Abstract: This paper describes the methods and simulation techniques used to verify the microarchitecture design and functional performance of the IBM POWER4 processor and the POWER4-based Regatta system. The approach was hierarchical, based on but considerably expanding the practice used for verification of the CMOS-based IBM S/390 Parallel Enterprise Server™ G4. For POWER4, verification began at the abstract, high-level design phase and continued throughout the designer and unit levels, the multi-unit level, and finally the multiple-chip system level. The abstract (high-level design) phase permitted early validation of the POWER4 processor design prior to its commitment to HDL. The designer and unit-level stages focused on ensuring the correctness of the microarchitectural components. Multiunitlevel verification, performed on storage and I/O components as well as on the processor, confirmed architectural compliance for each of the chips and subsystems. Finally, systemlevel verification tested multiprocessor coherence and system-level function, including processor-to-I/O communication and validation of multiple hardware configurations. In parallel with design and functional validation, verification of reliability functions, performance, and degraded configurations was also performed at most of the levels in the hierarchy.

New insights into carrier transport in n-MOSFETs

Abstract: This paper discusses recent experimental investigations of the relation between low-field effective mobility and effective injection velocity of electrons from the source into the channel, as manifested in current drive, of deeply scaled n-MOSFETs. It is first established that the effective velocity in electrostatically sound, "well-tempered" scaled devices, for example with drain-induced barrier lowering (DIBL) limited to 120 mV/V, is well below the theoretical fully ballistic injection velocity. This is consistent with the fact that, as the channel length is scaled and the longitudinal field increases, preservation of electrostatic integrity requires increasing transverse field, which leads to increased surface scattering and therefore decreased mobility. In addition, evidence is presented that the effective channel mobility in modern short-channel devices is further decreased, probably due to increased ionized dopant scattering in the heavily doped channel halos. Then a correlation range of 45-60% between effective injection velocity and low-field mobility is established experimentally in sub-50-nm-channel MOSFETs. All of these factors point to the possibility of increasing the performance of deeply scaled n-MOSFETs by pursuing enhanced channel-mobility device structures such as double-gate MOSFET, or materials such as strained Si on relaxed SiGe.

Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology

Abstract: The POWER4-based p690 systems offer the highest performance of the IBM eServer pSeries™ line of computers. Within the general-purpose UNIX® server market, they also offer the highest levels of concurrent error detection, fault isolation, recovery, and availability. High availability is achieved by minimizing component failure rates through improvements in the base technology, and through design techniques that permit hardand soft-failure detection, recovery, and isolation, repair deferral, and component replacement concurrent with system operation. In this paper, we discuss the faulttolerant design techniques that were used for array, logic, storage, and I/O subsystems for the p690. We also present the diagnostic strategy, fault-isolation, and recovery techniques. New features such as POWER4 synchronous machine-check interrupt, PCI bus error recovery, array dynamic redundancy, and minimum-element dynamic reconfiguration are described. The design process used to verify error detection, fault isolation, and recovery is also described.

An advanced multichip module (MCM) for high-performance UNIX servers

Abstract: In 2001, IBM delivered to the marketplace a high-performance UNIX?®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-?µm pads on 200-?µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm ?? 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

The microarchitecture of the IBM eServer z900 processor

Abstract: The recent IBM ESA/390 CMOS line of processors, from 1997 to 1999, consisted of the G4, G5, and G6 processors. The architecture they implemented lacked 64-bit addressability and had only a limited set of 64- bit arithmetic instructions. The processors also lacked data and instruction bandwidth, since they utilized a unified cache. The branch performance was good, but there were delays due to conflicts in searching and writing the branch target buffer. Also, the hardware data compression and decimal arithmetic performance, though good, was in demand by database and COBOL programmers. Most of the performance concerns regarding prior processors were due to area constraints. Recent technology advances have increased the circuit density by 50 percent over that of the G6 processor. This has allowed the design of several performance-critical areas to be revisited. The end result of these efforts is the IBM eServer z900 processor, which is the first high-end processor based on the new 64-bit z/Architecture™.

Why BiCMOS and SOI BiCMOS

Abstract: Silicon technology development is at a crossroads, following an exponential rate of progress for more than thirty years. While CMOS (complementary metal-oxide-semiconductor) will remain the backbone of digital logic, silicon technology will evolve in directions driven by system needs that are not met by CMOS alone. It is argued that BiCMOS (bipolar complementary metal-oxide-semiconductor), particularly SOI (silicon-on-insulator) BiCMOS, will emerge as an important technology platform for mixed-signal systems. The bipolar transistors will be used primarily for the rf (radio-frequency) and analog functions, while the CMOS will be used for most digital functions. The SOI substrate provides dc and ac isolation, as well as opportunities for further device and circuit innovation.

Land grid array sockets for server applications

Abstract: The design and performance of land grid array (LGA) sockets are discussed with respect to high-performance server applications. Motivations for the use of this technology are presented, and the specific challenges associated with its application are discussed from a mechanical perspective. A variety of mechanical performance considerations are identified for LGA socket technologies, and a detailed evaluation of competing socket-actuation designs is presented using finite element structural analysis. Some design approaches are shown to suffer from excessive mechanical flexure, which can consume the allowable range of motion of the contact, resulting in excessive contact load variation within the LGA. Statistical considerations for the mechanical deflections and tolerances that contribute to range-of-motion consumption are developed using Monte Carlo techniques, and a parametric study of the mechanical design variables that influence contact load variation within the LGA is presented.

Process requirements for continued scaling of CMOS: the need and prospects for atomic-level manipulation

Abstract: Since the advent of the Si-based integrated circuit, ever-increasing function has been available at reduced cost and with reduced consumption of power. This "semiconductor revolution" has been possible because semiconductor devices have the unique feature that as they become smaller they also become faster, consume less power, become cheaper per circuit, and enable more function per unit area of Si. As the basic device approaches atomic dimensions, it is not clear how far scaling can continue, which current processing technologies lack extendibility, and what innovative process technologies will emerge to take their place. Examination of some of the requirements set forth in the International Technology Roadmap for Semiconductors (ITRS) [1] will expose some of the process modules that are likely to limit scaling. Future work that might be developed to meet the needs of the CMOS roadmap will then be initiated. Among the processes being developed for future needs are a range of selflimited growth and etching reactions as well as other process steps that take advantage of atomic-level control and manipulation to enable new classes of substrate materials. The requirements that drive such a level of control, as well as the progress and prospects for these new techniques, are discussed in this paper.

Vertically scaled MOSFET gate stacks and junctions: how far are we likely to go?

Abstract: The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure SiO2 in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equivalent oxide thickness (EOT)-for example, HfO2, ZrO2, and their silicates. Nevertheless, considerable challenges lie ahead if we are to achieve an EOT of less than 0.5 nm. If only a single molecular interface layer of oxide is needed to preserve high channel mobility, it seems likely that an EOT of 0.4-0.5 nm would represent the physical limit of dielectric scaling, but even then with a very high leakage (∼105 A/cm2). For junctions, the main challenge lies in providing low parasitic series resistance as depths are scaled in order to reduce short-channel effects. Because contacts are ultimately expected to dominate the parasitic resistance, low-barrier-height contacts and/or very heavily doped junctions will be required. While ion implantation and annealing processes can certainly be extended to meet the junction-depth and series-resistance requirements for additional generations, alternative low-temperature deposition processes that produce either metastably or extraordinarily activated, abruptly doped regions seem better suited to solve the contact resistance problem.

Early analysis tools for system-on-a-chip design

Abstract: The paper describes the need for early analysis tools to enable developers of today's system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic® Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs and outline how this performance analysis capability can be integrated into an overall environment for efficient SoC design.

Development and attributes of z/Architecture

Abstract: The IBM z/Architecture™ instruction set architecture (ISA) is an extension of the IBM Enterprise Systems Architecture/390® (ESA/390) ISA and features 64-bit general registers, 64-bit operations, and 64-bit virtual and real addressing. In addition, z/Architecture includes new instructions to optimize the handling of modern multi-byte character encodings and to improve the performance of programs written in high-level languages. It provides compatibility for ESA/390 application programs and increases the ease of development of new application programs. This paper presents an overview of the interesting aspects of z/Architecture and some of the associated decisions and tradeoffs made in its development.

Effect of increasing chip density on the evolution of computer architectures

Abstract: Trends in lithography and process technology indicate that billion-transistor computer chips will be possible well before the end of the decade. Such a large number of transistors could be used to implement dynamic learning techniques to improve the performance of a processor for many applications. However, the efficiency of use of transistors in this manner is not high. A more attractive use of the available transistors is to bring more of the entire system onto the chip, and this paper examines two different approaches for doing so. The first involves bringing memory closer to the processors in a symmetric multiprocessor cell, and using these cells in a regular organization with a programmable interconnection to create powerful computers. The second involves integration on the same chip of varied structures such as processors, DRAM, sensors, and transducers, which in the past required different processing capabilities-commonly referred to as the System-on-a-Chip approach. The paper describes the exciting options offered by both approaches and discusses the implications of each for programming and tool development.

System control structure of the IBM eServer z900

Abstract: As computer systems become more complex, the use of embedded controllers for initializing and maintaining system operation is becoming increasingly prevalent. In the IBM eServer z900, a new control approach was introduced. This paper discusses why its introduction was necessary and outlines its associated, key technological and economic innovations. In particular, the following topics are addressed: service subsystem topology, hardware elements for performing system control, hardware abstraction, object-oriented framework for control, and internetworking of system control microprocessors.

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering

Abstract: This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM third-generation embedded dynamic random-access memory (DRAM) for the IBM Blue Logic® 0.11-µm application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamental DRAM core function, user interface, test, and diagnosis. Macro operation and organization are detailed and contrasted with traditional DRAM designs. The use of BIST, a key enabler for embedded DRAM, is discussed while highlighting innovations required by the embedded DRAM.

z/CECSIM: an efficient and comprehensive microcode simulator for the IBM eServer z900

Abstract: An IBM eServer zSeries™ system uses various types of microcode (firmware) that implement functions such as the execution of complex instructions in the CPUs, I/O operations performed by the system assist processors (SAPs), the management of logical partitions (LPARs), and control by the support element (SE). Each microcode component must be verified by itself and in conjunction with the others. Tight development schedules and a very limited supply of expensive engineering hardware make it desirable to perform this verification in a simulation environment. For the development of the z900, a new microcode simulator, the z/CECSIM (Central Electronic Complex Simulator), was successfully implemented. Several microcode components are connected in a single simulation environment, thereby allowing an unprecedented amount of development, integration, and testing without the use of engineering hardware. z/CECSIM creates a virtual zSeries CEC on VM/ESA® or z/VM™ that allows the simulation of zSeries microcode. It executes the instruction stream as completely as possible on the underlying hardware. Only instructions that are newly introduced with the system being developed or that perform a microcode-internal function are simulated. Additional software models mimic the behavior of I/O and coupling channels. An optional SE connection allows verification of interactions between the CEC and its support element.

Issues and strategies for the physical design of system-on-a-chip ASICs

Abstract: The density and performance of advanced silicon technologies have made system-on-a-chip ASICs possible. SoCs bring together a diverse set of functions and technology features on a single die of enormous complexity. The physical design of these complex ASICs requires a rich set of functional elements that integrate efficiently with a set of design flows and tools productive enough to meet product requirements successfully, without consuming more time or design resources than a simpler design. The architecture described, including functional libraries and physical design conventions, enables the creation of multiple SoC ASIC designs from a common infrastructure that addresses silicon integration, electrical robustness, and packaging challenges. An implementation strategy follows from this design infrastructure that includes hierarchical design concepts, placement, routing, and verification processes.

IBM eServer z900 I/O subsystem

Abstract: The IBM eServer z900 is the first in a generation of future eServers that continues its leadership via a new I/O subsystem with enhancements in capability, performance, configuration management, and qualities of service. Significant features of the I/O subsystem are included to support the 64-bit z/Architecture™ and configuration-management enhancements [e.g., assignable channel path identifiers (CHPIDs) and dynamic channel path management (DCM)]. A 1GB/s self-timed interface (STI), I/O infrastructure, and I/O card cage are described which support the high-bandwidth I/O (e.g., FICON™, Ethernet). These improvements yield enhanced configuration flexibility and connectivity, as well as reliability, availability, and serviceability (RAS), while providing for future bandwidth growth. The various types of I/O ports supported by the IBM eServer z900 platform are also discussed. A common I/O platform is discussed which has been used to provide a uniform, high-bandwidth attachment of industry-standard peripheral computer interface (PCI) cards, while maintaining the leadership functionality and RAS of the eServer zSeries™. A high-density (16-port) ESCON® I/O card has been designed by exploiting IBM advanced CMOS and state-of-the-art fiber optic technologies. Finally, a high-performance, high-density intersystem channel (ISC-3) coupling link I/O card has been developed for the IBM eServer z900 by leveraging advanced technology and packaging techniques.

RAS design for the IBM eServer z900

Abstract: The IBM eServer zSeries™ Model 900, or z900, has been designed with major enhancements for hardware reliability, availability, and serviceability (RAS) in support of the zSeries RAS strategy, the eServer self-management technologies, and the z900 design objective of continuous reliable operation. The eServer self-management technologies enable the server to protect itself, to detect and recover from errors, to change and configure itself, and to optimize itself, in the presence of problems and changes, for maximum performance with minimum outside intervention. From the RAS perspective, the longstanding RAS strategy for the IBM S/390® and now the zSeries has provided an excellent foundation for self management. This paper describes the z900 RAS enhancements and how they strengthen the RAS strategy building blocks and provide a basis for autonomic computing.