Transparent electronic devices formed on flexible substrates are expected to meet emerging technological demands where silicon-based electronics cannot provide a solution. Examples of active flexible applications include paper displays and wearable computers1. So far, mainly flexible devices based on hydrogenated amorphous silicon (a-Si:H)2,3,4,5 and organic semiconductors2,6,7,8,9,10 have been investigated. However, the performance of these devices has been insufficient for use as transistors in practical computers and current-driven organic light-emitting diode displays. Fabricating high-performance devices is challenging, owing to a trade-off between processing temperature and device performance. Here, we propose to solve this problem by using a novel semiconducting material—namely, a transparent amorphous oxide semiconductor from the In-Ga-Zn-O system (a-IGZO)—for the active channel in transparent thin-film transistors (TTFTs). The a-IGZO is deposited on polyethylene terephthalate at room temperature and exhibits Hall effect mobilities exceeding 10 cm2 V-1 s-1, which is an order of magnitude larger than for hydrogenated amorphous silicon. TTFTs fabricated on polyethylene terephthalate sheets exhibit saturation mobilities of 6–9 cm2 V-1 s-1, and device characteristics are stable during repetitive bending of the TTFT sheet.

Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

Organic thin-film transistors (OTFTs) have lived to see great improvements in recent years. This review presents new insight into conduction mechanisms and performance characteristics, as well as opportunities for modeling properties of OTFTs. The shifted focus in research from novel chemical structures to fabrication technologies that optimize morphology and structural order is underscored by chapters on vacuum-deposited and solution-processed organic semiconducting films. Finally, progress in the growing field of the n-type OTFTs is discussed in ample detail. The Figure, showing a pentacene film edge on SiO2, illustrates the morphology issue.

Organic Thin Film Transistors for Large Area Electronics

Graphene’s success has shown that it is possible to create stable, single and few-atom-thick layers of van der Waals materials, and also that these materials can exhibit fascinating and technologically useful properties. Here we review the state-of-the-art of 2D materials beyond graphene. Initially, we will outline the different chemical classes of 2D materials and discuss the various strategies to prepare single-layer, few-layer, and multilayer assembly materials in solution, on substrates, and on the wafer scale. Additionally, we present an experimental guide for identifying and characterizing single-layer-thick materials, as well as outlining emerging techniques that yield both local and global information. We describe the differences that occur in the electronic structure between the bulk and the single layer and discuss various methods of tuning their electronic properties by manipulating the surface. Finally, we highlight the properties and advantages of single-, few-, and many-layer 2D materials in...

/pdf/progress-challenges-and-opportunities-in-two-dimensional-1sweg4hljr.pdf

Progress, Challenges, and Opportunities in Two-Dimensional Materials Beyond Graphene

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >

/pdf/low-power-cmos-digital-design-52v6aautu5.pdf

Low-power CMOS digital design

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

/pdf/device-scaling-limits-of-si-mosfets-and-their-application-299ftwsxth.pdf

Device scaling limits of Si MOSFETs and their application dependencies

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

Quantum-mechanical modeling of electron tunneling current from the quantized inversion layer of ultra-thin-oxide (<40 /spl Aring/) nMOSFET's is presented, together with experimental verification. An accurate determination of the physical oxide thickness is achieved by fitting experimentally measured capacitance-versus-voltage curves to quantum-mechanically simulated capacitance-versus-voltage results. The lifetimes of quasibound states and the direct tunneling current are calculated using a transverse-resonant method. These results are used to project an oxide scaling limit of 20 /spl Aring/ before the chip standby power becomes excessive due to tunneling currents,.

Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's

Beginning with a brief review of CMOS scaling trends from 1 µm to 01 µm, this paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length Both the standby power and the active power of a processor chip will increase precipitously below the 01-µm or 100-nm technology generation To extend CMOS scaling to the shortest channel length possible while still gaining significant performance benefit, an optimized, vertically and laterally nonuniform doping design (superhalo) is presented It is projected that room-temperature CMOS will be scaled to 20-nm channel length with the superhalo profile Low-temperature CMOS allows additional design space to further extend CMOS scaling to near 10 nm

Yuan Taur

Papers

Fundamentals of Modern VLSI Devices

Device scaling limits of Si MOSFETs and their application dependencies

CMOS scaling into the nanometer regime

Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's

CMOS design near the limit of scaling