Journal ArticleDOI
SOI technology for the GHz era
TLDR
The reasons for performance improvement with SOI, and its scalability to the 0.1-µm generation and beyond are described, which is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.Abstract:
Silicon-on-insulator (SOI) CMOS offers a 20–35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-µm generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-µm generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-µm generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.read more
Citations
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Journal ArticleDOI
Three-dimensional integrated circuits
Anna W. Topol,D.C. La Tulipe,L. Shi,David J. Frank,K. Bernstein,Steven E. Steen,Arvind Kumar,G. U. Singco,A. M. Young,K. W. Guarini,Meikei Ieong +10 more
TL;DR: The process steps and design aspects that were developed at IBM to enable the formation of stacked device layers are reviewed, including the descriptions of a glass substrate process to enable through-wafer alignment and a single-damascene patterning and metallization method for the creation of high-aspect-ratio capability.
Journal ArticleDOI
Lithography and Other Patterning Techniques for Future Electronics
TL;DR: In this paper, the authors focus on the benefits of using ICs at the 22-nm node and beyond, and no shortage of ideas on how to accomplish this, although it is not clear that optics will be the most economical in this range; extreme ultraviolet is still the official front runner, and electron beam lithography, which has demonstrated minimum features less than 10 nm wide, continues to be developed both for mask making and for directly writing on the wafer (also known as ldquomaskless lithographyrdquo).
Lithography and Other Patterning Techniques for Future Electronics As integrated circuits continue to go smaller, laying down circuit patterns on semiconductor material becomes more expensive and new techniques are needed.
R. Fabian Pease,Stephen Y. Chou +1 more
TL;DR: The benefits of continuing to be able to manufacture electronics at the 22-nm node and beyond appear to justify the investment, and there is no shortage of ideas on how to accomplish this.
Patent
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
TL;DR: In this article, a planar SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer, followed by a partially-depleted SOI (PD-SOI) layer.
References
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Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Book
Silicon-on-Insulator Technology: Materials to VLSI
TL;DR: In this paper, the authors present a set of techniques for defect detection in SOI materials, including the following: 2.1.1 Silicon-on-Zirconia (SOZ), 2.2.2 E-beam recrystallization, 2.3.3, 3.4.4, and 3.5.5 Other defect assessment techniques.
Proceedings ArticleDOI
Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
TL;DR: In this article, the authors investigate scaling challenges and outline device design requirements needed to support high performance low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm.
Proceedings ArticleDOI
Physical design of a fourth-generation POWER GHz microprocessor
Carl J. Anderson,John George Petrovick,J. Keaty,James D. Warnock,G. Nussbaum,J.M. Tendier,Craig R. Carter,Shao-Fu S. Chu,Joachim Gerhard Clabes,Jack DiLullo,P. E. Dudley,P. Harvey,Byron L. Krauter,J. LeBlanc,Pong-Fei Lu,Bradley McCredie,G. Plum,Phillip J. Restle,Steve Runyon,Michael R. Scheuermann,S. Schmidt,J. Wagoner,R. Weiss,S. Weitzel,B. A. Zoric +24 more
TL;DR: The fourth-generation POWER processor as discussed by the authors contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP.
Proceedings ArticleDOI
Partially-depleted SOI technology for digital logic
Ghavam G. Shahidi,Atul C. Ajmera,Fariborz Assaderaghi,R. Bolam,Effendi Leobandung,Werner A. Rausch,D. Sankus,Dominic J. Schepis,Lawrence F. Wagner,Kun Wu,Bijan Davari +10 more
TL;DR: In this paper, the partially depleted (PD) silicon on insulator (SOI) technology results in 20-35% performance gain over a comparable bulk technology and a number of SOI-unique effects that complicate device and circuit design are discussed, along with possible remedies.