High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

International Symposium on Quality Electronic Design

The ISPD~2015 placement-contest benchmarks include all the detailed pin, cell, and wire geometry constraints from the 2014 release, plus(a) added fence regions and placement blockages,(b) altered netlists including fixed macro blocks,(c) reduced standard cell area utilization via larger floorplan outlines, and(d)] specified upper limits on local cell-area density.Compared to the 2014 release, these new constraints add realism and increase the difficulty of producing detail-routable wirelength-driven placements.

ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for two-dimensional circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits while considering different forms of vertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated in vertical integration due to the limited number of package pins, the distance of these pins from other planes within the 3-D system, and the impedance characteristics of the through silicon vias (TSVs). In addition to these dedicated networks, global signaling techniques that incorporate the diverse traits of complex 3-D systems are required. One possible approach, potentially significantly reducing the complexity of interconnect issues in 3-D circuits, is 3-D networks-on-chip (NoC). Design methodologies that exploit the diversity of 3-D structures to further enhance the performance of multiplane integrated systems are necessary. The longest interconnects within a 3-D circuit are those interconnects comprising several TSVs and traversing multiple physical planes. Consequently, minimizing the delay of the interplane nets is of great importance. By considering the nonuniform impedance characteristics of the interplane interconnects while placing the TSVs, the delay of these nets is decreased. In addition, the difference in electrical behavior between the horizontal and vertical interconnects suggests that asymmetric structures can be useful candidates for distributing the clock signal within a 3-D circuit. A 3-D test circuit fabricated with a 180 nm silicon-on-insulator (SOI) technology, manufactured by MIT Lincoln Laboratories, exploring several clock distribution topologies is described. Correct operation at 1 GHz has been demonstrated. Several 3-D NoC topologies incorporating dissimilar 3-D interconnect structures are reviewed as a promising solution for communication limited systems-on-chip (SoC). Appropriate performance models are described to evaluate these topologies. Several forms of vertical integration, such as system-in-package and different candidate technologies for 3-D circuits, such as SOI, are considered. The techniques described in this paper address fundamental interconnect structures in the 3-D design process. Several interesting research problems in the design of 3-D circuits are also discussed.

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits : Vertical integration is a novel communications paradigm where interconnect design is a primary focus

The Nesterov’s method approach to analytic placement has recently demonstrated strong solution quality and scalability. We dissect the previous implementation strategy and show that solution quality can be significantly improved using two levers: 1) constraint-oriented local smoothing and 2) dynamic step size adaptation. We propose a new density function that comprehends local overflow of area resources; this enables a constraint-oriented local smoothing at per-bin granularity. Our improved dynamic step size adaptation automatically determines step size and effectively allocates optimization effort to significantly improve solution quality without undue runtime impact. Our resulting global placement tool, RePlAce, achieves an average of 2.00% half-perimeter wirelength (HPWL) reduction over all best known ISPD-2005 and ISPD-2006 benchmark results, and an average of 2.73% over all best known modern mixed-size (MMS) benchmark results, without any benchmark-specific code or tuning. We further extend our global placer to address routability, and achieve on average 8.50%–9.59% scaled HPWL reduction over previous leading academic placers for the DAC-2012 and ICCAD-2012 benchmark suites. To our knowledge, RePlAce is the first work to achieve superior solution quality across all the ISPD-2005, ISPD-2006, MMS, DAC-2012, and ICCAD-2012 benchmark suites with a single global placement engine.

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement

Circuit optimization is essential to minimize power consumption of designs while satisfying timing constraints. The CAD problem focused on in the ISPD-2012 Contest is simultaneous gate sizing and threshold voltage assignment. In this paper, we describe an overview of the contest objectives and the provided benchmark suite. Furthermore, some details are provided in terms of the standard cell library, timing models, and the evaluation metrics of the ISPD-2012 Contest.

The ISPD-2012 discrete cell sizing contest and benchmark suite

Gate sizing and threshold voltage selection is an important step in the VLSI design process to optimize power and performance of a given netlist. In this paper, we provide an overview of the ISPD-2013 Discrete Cell Sizing Contest. Compared to the ISPD-2012 Contest, we propose improvements in terms of the benchmark suite and the timing models utilized. In this paper, we briefly describe the contest, and provide some details about the standard cell library, benchmark suite, timing infrastructure and the evaluation metrics.

An improved benchmark suite for the ISPD-2013 discrete cell sizing contest

This paper evaluates and compares different clock architectures such as mesh, tree and their hybrids, on several industrial designs. The goal of our study is to gain a quantitative understanding of engineering trade-offs between different architectures with respect to clock skew, latency, timing uncertainty, and power. This understanding will lead to guidelines for determining the best clock architecture for the design specification and constraints. To the best of our knowledge, no work has been published on evaluating and comparing these architectures on real industrial designs. Our study shows that mesh-based architectures are better than tree architectures for skew (\le 1ps skew) and are more robust to variations (18% reduction in timing uncertainty as compared to tree). The power penalty associated with a mesh as compared to a tree was found to be between 10-40%. Use of multiple meshes can help reduce the power penalty.

Clock Distribution Architectures: A Comparative Study

Mesh architectures are used for distributing critical global signals on a chip such as clock and power/ground. The inherent redundancy created by loops present in the mesh smooths out undesirable variations between signal nodes spatially distributed over the chip. However, one outstanding problem with mesh architectures is the difficulty in analyzing them with sufficient accuracy. In this paper, we present a new sliding window-based scheme to analyze the latency in clock meshes. We show that for small meshes, our scheme comes within 1% of the SPICE simulation of the complete mesh with respect to clock latency. Our scheme is ideally suited for distributed- or grid-computing. We show large design instances where SPICE could not finish, whereas our scheme could complete the analysis in less than 2 hours.

A sliding window scheme for accurate clock mesh analysis

High-performance clock distribution has been a challenge for nearly three decades. During this time, clock synthesis tools and algorithms have strove to address a myriad of important issues helping designers to create faster, more reliable, and more power efficient chips. This work provides a complete discussion of the high-performance ASIC clock distribution using information gathered from both leading industrial clock designers and previous research publications. While many techniques are only briefly explained, the references summarize the most influential papers on a variety of topics for more in-depth investigation. This article also provides a thorough discussion of current issues in clock synthesis and concludes with insight into future research and design challenges for the community at large.

Gustavo Wilke

Papers

The ISPD-2012 discrete cell sizing contest and benchmark suite

An improved benchmark suite for the ISPD-2013 discrete cell sizing contest

Clock Distribution Architectures: A Comparative Study

A sliding window scheme for accurate clock mesh analysis

Revisiting automated physical synthesis of high-performance clock networks