A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.

Programmable interconnect architecture

A new model of random graphs – random intersection graphs – is introduced. In this model, vertices are assigned random subsets of a given set. Two vertices are adjacent provided their assigned sets intersect. We explore the evolution of random intersection graphs by studying thresholds for the appearance and disappearance of small induced subgraphs. An application to gate matrix circuit design is presented.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S0963548398003459

On Random Intersection Graphs: The Subgraph Problem

This paper proposes a new layout method for high-speed VLSI circuits in single-poly and double-metal MOS technology. With emphasis on the speed performance, our Metal-Metal Matrix (M /sup 3/) layout method employs maximal use of metal interconnections while restricting delay-consuming polysilicon or polycide features only to form MOS transistor gates or to connect the same type of transistor gates with common input signals. M /sup 3/ layout is also amenable to submicron technology trends and existing CAD tools for single-poly and single-metal chip assembly and routing. Our layout studies indicate that M /sup 3/ is particularly appealing to high-speed dynamic CMOS circuits in view of packing density and speed performance. This new structure has not been experimented with VLSI chip fabrication yet and awaits empirical verification.

Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout

Graph Problems Related to Gate Matrix Layout and PLA Folding. This paper gives a survey on graph problems occuring in linear VLSI layout architectures such as gate matrix layout, folding of programmable logic arrays, and Weinberger arrays. These include a variety of mostly independently investigated graph problems such as augmentation of a given graph to an interval graph with small clique size, node search of graphs, matching problems with side constraints, and other. We discuss implications of graph theoretic results for the VLSI layout problems and survey new research directions. New results presented include NP-hardness of gate matrix layout on chordal graphs, efficient algorithms for trees, cographs, and certain chordal graphs, Lagrangean relaxation and approximation algorithms based on on-line interval graph augmentation.

Graph Problems Related to Gate Matrix Layout and PLA Folding

A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected.

Reconfigurable programmable interconnect architecture

A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of intersecting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.

A dense gate matrix layout method for MOS VLSI

A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of interacting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.

H.-F.S. Law

Papers

A dense gate matrix layout method for MOS VLSI

A Dense Gate Matrix Layout Method for MOS VLSI