Journal ArticleDOI
A dense gate matrix layout method for MOS VLSI
A.D. Lopez,H.-F.S. Law +1 more
TLDR
A rapid and systematic method for performing chip layout of VLSI circuits is described, which utilizes the configuration of a matrix composed of interacting rows and columns to provide transistor placement and interconnections.Abstract:
A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of intersecting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.read more
Citations
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Journal ArticleDOI
On Random Intersection Graphs: The Subgraph Problem
TL;DR: In this paper, a new model of random graphs called random intersection graphs is introduced, where vertices are assigned random subsets of a given set and two nodes are adjacent provided their assigned sets intersect.
Journal ArticleDOI
Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout
TL;DR: The Metal-Metal Matrix (M /sup 3/) layout method employs maximal use of metal interconnections while restricting delay-consuming polysilicon or polycide features only to form MOS transistor gates or to connect the same type of transistor gates with common input signals.
Book ChapterDOI
Graph Problems Related to Gate Matrix Layout and PLA Folding
TL;DR: A survey on graph problems occuring in linear VLSI layout architectures such as gate matrix layout, folding of programmable logic arrays, and Weinberger arrays and results presented include NP-hardness of gate Matrix layout on chordal graphs, efficient algorithms for trees, cographs, and certain chordal graph graphs, Lagrangean relaxation and approximation algorithms based on on-line interval graph augmentation.
Journal ArticleDOI
On minimizing width in linear layouts
TL;DR: The problem of determining the cutwidth of a graph, called the Min Cut Linear Arrangement problem, has applications in VLSI, for example in the minimization of interconnection channels in Weinberger arrays.
Journal ArticleDOI
Nonconstructive advances in polynomial-time complexity
TL;DR: This paper illustrates how recent advances in graph theory and graph algorithms dramatically alter the situation for classifying problems as decidable in polynomial time by nonconstructively proving only the existence ofPolynomial-time decision algorithms.
References
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Journal ArticleDOI
MOTIS-An MOS timing simulator
TL;DR: In this paper, a new circuit simulator is described which combines the gate-to-gate signal propagation technique used in logic simulators with detailed device representation and circuit analysis at the gate level.
Journal ArticleDOI
Large Scale Integration of MOS Complex Logic: A Layout Method
TL;DR: A unique but rather simple layout method is described that combines layout standardization with high circuit density generally expected from customized layout, at the same time, the design of the personality (the desired interconnection pattern) is simplified, while using a single layer of metallization.
Proceedings ArticleDOI
LTX-A system for the directed automatic design of LSI circuits
TL;DR: LTX is a minicomputer-based design system for large-scale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design.
Proceedings ArticleDOI
Versatile Mask Generation Techniques for Custom Microelectronic Devices
TL;DR: These mask generation techniques provide a cost-effective means of generating mask sets for custom microelectronic devices while also providing device design portability and is ideally suited for process experimentation.
Proceedings ArticleDOI
Block and track method for automated layout generation of MOS-LSI arrays
TL;DR: An automated layout program with a block and track concept that can generate composite-patterns for single-chip calculator MOS-LSI arrays within 600 seconds computing time with manual-comparable chip areas will be described.