H
Hadi Parandeh-Afshar
Researcher at École Polytechnique Fédérale de Lausanne
Publications - 35
Citations - 480
Hadi Parandeh-Afshar is an academic researcher from École Polytechnique Fédérale de Lausanne. The author has contributed to research in topics: Field-programmable gate array & Adder. The author has an hindex of 11, co-authored 35 publications receiving 444 citations. Previous affiliations of Hadi Parandeh-Afshar include University of Tehran & École Normale Supérieure.
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Proceedings ArticleDOI
Efficient synthesis of compressor trees on FPGAs
TL;DR: This paper presents the first method to successfully synthesize compressor trees on LUT-based FPGAs using generalized parallel counters (GPCs) and a heuristic, presented within, constructs a compressor tree from a library of GPCs that can efficiently be implemented on the target FPGA.
Proceedings ArticleDOI
Exploiting fast carry-chains of FPGAs for designing compressor trees
TL;DR: This paper demonstrates that the carry chains can be used to build compressor trees, i.e., multi-input addition circuits used for parallel accumulation and partial product reduction for parallel multipliers implemented in FPGA logic.
Journal ArticleDOI
Compressor tree synthesis on commercial high-performance FPGAs
TL;DR: The experimental results show that the use of compressor trees can reduce critical path delay by 33% and 45% respectively, compared to adder trees synthesized on the Xilinx Virtex-5 and Altera Stratix III FPGAs.
Proceedings ArticleDOI
Improving synthesis of compressor trees on FPGAs via integer linear programming
TL;DR: A new solution to the mapping problem based on integer linear programming reduced the delay of the compressor tree by 32% on average and reduced the area by 3% compared to an adder tree.
Journal ArticleDOI
Improving FPGA Performance for Carry-Save Arithmetic
TL;DR: The field programmable counter array (FPCA) is introduced, an accelerator for carry-save arithmetic intended for integration into an FPGA as an alternative to DSP blocks and improves performance, area utilization, and energy consumption compared with soft FPGAs.