van der Waals (vdW) heterojunctions composed of two-dimensional (2D) layered materials are emerging as a solid-state materials family that exhibits novel physics phenomena that can power a range of electronic and photonic applications. Here, we present the first demonstration of an important building block in vdW solids: room temperature Esaki tunnel diodes. The Esaki diodes were realized in vdW heterostructures made of black phosphorus (BP) and tin diselenide (SnSe2), two layered semiconductors that possess a broken-gap energy band offset. The presence of a thin insulating barrier between BP and SnSe2 enabled the observation of a prominent negative differential resistance (NDR) region in the forward-bias current–voltage characteristics, with a peak to valley ratio of 1.8 at 300 K and 2.8 at 80 K. A weak temperature dependence of the NDR indicates electron tunneling being the dominant transport mechanism, and a theoretical model shows excellent agreement with the experimental results. Furthermore, the bro...

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Esaki Diodes in van der Waals Heterojunctions with Broken-Gap Energy Band Alignment

http://cmliris.harvard.edu/assets/science291_851.pdf

Functional Nanoscale Electronic Devices Assembled Using Silicon Nanowire Building Blocks

We investigate electron and hole mobilities in strained silicon nanowires (Si NWs) within an atomistic tight-binding framework. We show that the carrier mobilities in Si NWs are very responsive to strain and can be enhanced or reduced by a factor >2 (up to 5×) for moderate strains in the ±2% range. The effects of strain on the transport properties are, however, very dependent on the orientation of the nanowires. Stretched ⟨100⟩ Si NWs are found to be the best compromise for the transport of both electrons and holes in ≈10 nm diameter Si NWs. Our results demonstrate that strain engineering can be used as a very efficient booster for NW technologies and that due care must be given to process-induced strains in NW devices to achieve reproducible performances.

Effects of strain on the carrier mobility in silicon nanowires.

Review for order reduction based on proper orthogonal decomposition and outlooks of applications in mechanical systems

In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT presents superior transconductance (Gm), early voltage (VEA), and intrinsic gain (GmRO) compared with SMG DGJLT. The values are further improved for DMG-SP DGJLT, because high- k spacer enhances the fringing electric fields through the spacer.

A Dual-Material Gate Junctionless Transistor With High- $k$ Spacer for Enhanced Analog Performance

A dual-material-gate junctionless nanowire transistor (DMG-JNT) is proposed in this paper. Its characteristic is demonstrated and compared with a generic single-material-gate JNT using 3-D numerical simulations. The results show that the DMG-JNT has a number of desirable features, such as high ON-state current, a large ON/OFF current ratio, improved transconductance Gm, high unity-gain frequency fT, high maximum oscillation frequency fMAX, and reduced drain-induced barrier lowering. The effects of different control gate ratios Ra and varied work-function differences between the two gates are studied. Finally, the optimization of Ra and the work-function difference for the proposed DMG-JNT is presented.

A Junctionless Nanowire Transistor With a Dual-Material Gate

This letter describes the formation of one-time-programmable (OTP) memory using standard contact fuse and polysilicon diode in a standard CMOS technology. Programming of the contact fuse is achieved by applying a high current pulse to destroy the contact. Compared with other existing OTP technologies, the proposed approach has the advantage of zero additional mask, no additional processing step, compact structure, and low programming voltage. The described OTP has been demonstrated in a 0.18-μm CMOS technology from TSMC with a cell size of 2.33 μm2 . The contact fuse can be programmed with a voltage of 3 V and a current of 2.4 mA.

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

In this paper, an analytical potential-based model in the subthreshold regime for short-channel junctionless cylindrical surrounding-gate MOSFETs is proposed as the source/drain depletion effect considered. The threshold voltage ( $V_{\textrm {th}}$ ), subthreshold slope, and drain-induced barrier lowering are also correspondingly derived, which give explicit explanations of the short-channel effects on junctionless MOSFETs in the subthreshold regime. The compact model is verified by the numerical simulation, and the results match well.

A Compact Model of Subthreshold Current With Source/Drain Depletion Effect for the Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs

A new model to capture the physics of short channel double-gate junctionless transistor (DGJT) has been developed. By solving the 2-D Poisson’s equation, the channel potential solution is obtained for both the physical channel and the dynamic channel extension to the source and drain. This dynamic change in channel boundary in DGJT has a strong impact on the performance of junctionless transistor, especially at reduced channel length. Based on the channel potential solution, a smooth and continuous drain current model is derived from Pao–Sah’s dual integral. This model is valid for all operation modes, including full depletion, partial depletion, and accumulation. Extensive comparison with numerical simulation has been performed to validate model in both the long channel and short channel regimes.

A Short Channel Double-Gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect

Uniaxial strain effects on electron ballistic transport in extremely scaled gate-all-around nanowire MOSFETs with both [100] and [110] orientations are investigated in this paper. Band structures of nanowires without and with strain are calculated using the empirical sp3d5s* tight-binding model. The top-of-the-barrier model is utilized to simulate the electron ballistic transport. It is found that uniaxial [110] strain reduces the electron transport mass, but its effect gradually decreases and becomes insignificant when the dimension of the nanowire is scaled. In addition to existing band splitting caused by quantum confinement, [100] and [110] tensile strains induce further band splitting. Hence, the impact of the strain effects depends on whether the nanowire operates in the nondegenerated or degenerated mode. Simulation results show that uniaxial strain effects are more significant in [110] nanowires. The impact of surface orientation can still be observed even in deeply scaled nanowires.

Haijun Lou

Papers

A Junctionless Nanowire Transistor With a Dual-Material Gate

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

A Compact Model of Subthreshold Current With Source/Drain Depletion Effect for the Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs

A Short Channel Double-Gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect

Uniaxial Strain Effects on Electron Ballistic Transport in Gate-All-Around Silicon Nanowire MOSFETs