International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Efficient Carbon Nanotube Photodiodes A single photon absorbed in a single-walled carbon nanotube device can generate multiple unbound particles carrying an electric charge. Gabor et al. (p. 1367) report that in such a device at low temperatures, excitation with light of increasing energy leads to well-defined stepwise increases in current. Interestingly, because of the unique band structure of carbon nanotubes, this behavior is analogous to particle-antiparticle creation commonly observed in high-energy particle physics. These observations point to the promise of investigations in other nanoscale carbon systems, such as graphene, and could lead to numerous applications, including highly sensitive photon detection and ultra-efficient photovoltaics. The decay of photoexcited electrons in a carbon nanotube device creates multiple pairs of charge carriers. We observed highly efficient generation of electron-hole pairs due to impact excitation in single-walled carbon nanotube p-n junction photodiodes. Optical excitation into the second electronic subband E22 leads to striking photocurrent steps in the device I-VSD characteristics that occur at voltage intervals of the band-gap energy EGAP/e. Spatially and spectrally resolved photocurrent combined with temperature-dependent studies suggest that these steps result from efficient generation of multiple electron-hole pairs from a single hot E22 carrier. This process is both of fundamental interest and relevant for applications in future ultra-efficient photovoltaic devices.

https://www.lassp.cornell.edu/lassp_data/mceuen/homepage/Publications/Gabor_Science_2009_supmat.pdf

Supporting Online Material for Extremely Efficient Multiple Electron-Hole Pair Generation in Carbon Nanotube Photodiodes

This paper reviews the current state of research in carbon-based nanomaterials, particularly the one-dimensional (1-D) forms, carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), whose promising electrical, thermal, and mechanical properties make them attractive candidates for next-generation integrated circuit (IC) applications. After summarizing the basic physics of these materials, the state of the art of their interconnect-related fabrication and modeling efforts is reviewed. Both electrical and thermal modeling and performance analysis for various CNT- and GNR-based interconnects are presented and compared with conventional interconnect materials to provide guidelines for their prospective applications. It is shown that single-walled, double-walled, and multiwalled CNTs can provide better performance than that of Cu. However, in order to make GNR interconnects comparable with Cu or CNT interconnects, both intercalation doping and high edge-specularity must be achieved. Thermal analysis of CNTs shows significant advantages in tall vias, indicating their promising application as through-silicon vias in 3-D ICs. In addition to on-chip interconnects, various applications exploiting the low-dimensional properties of these nanomaterials are discussed. These include chip-to-packaging interconnects as well as passive devices for future generations of IC technology. Specifically, the small form factor of CNTs and reduced skin effect in CNT interconnects have significant implications for the design of on-chip capacitors and inductors, respectively.

Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects

Nanoelectromechanical (NEM) switches are similar to conventional semiconductor switches in that they can be used as relays, transistors, logic devices and sensors. However, the operating principles of NEM switches and semiconductor switches are fundamentally different. These differences give NEM switches an advantage over semiconductor switches in some applications--for example, NEM switches perform much better in extreme environments--but semiconductor switches benefit from a much superior manufacturing infrastructure. Here we review the potential of NEM-switch technologies to complement or selectively replace conventional complementary metal-oxide semiconductor technology, and identify the challenges involved in the large-scale manufacture of a representative set of NEM-based devices.

Nanoelectromechanical contact switches

Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utilization wall forces designers to ensure that, at any point in time, large fractions of their chips are effectively dark or dim silicon, i.e., either idle or significantly underclocked. As exponentially larger fractions of a chip's transistors become dark, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift is driving a new class of architectural techniques that “spend” area to “buy” energy efficiency. All of these techniques seek to introduce new forms of heterogeneity into the computational stack. We envision that ultimately we will see widespread use of specialized architectures that leverage these techniques in order to attain orders-of-magnitude improvements in energy efficiency. However, many of these approaches also suffer from massive increases in complexity. As a result, we will need to look towards developing pervasively specialized architectures that insulate the hardware designer and the programmer from the underlying complexity of such systems. In this paper, I discuss four key approaches — the four horsemen — that have emerged as top contenders for thriving in the dark silicon age. Each class carries with its virtues deep-seated restrictions that requires a careful understanding of the underlying tradeoffs and benefits.

Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse

This paper highlights and experimentally verifies a new source of random threshold-voltage (V_th) fluctuation in emerging metal-gate transistors and proposes a statistical framework to investigate its device and circuit-level implications. The new source of variability, christened work-function (WF) variation (WFV), is caused by the dependence of metal WF on the orientation of its grains. The experimentally measured data reported in this paper confirm the existence of such variations in both planar and nonplanar high-k metal-gate transistors. As a result of WFV, the WFs of metal gates are statistical distributions instead of deterministic values. In this paper, the key parameters of such WF distributions are analytically modeled by identifying the physical dimensions of the devices and properties of materials used in the fabrication. It is shown that WFV can be modeled by a multinomial distribution where the key parameters of its probability distribution function can be calculated in terms of the aforementioned parameters. The analysis reveals that WFV will contribute a key source of V_th variability in emerging generations of metal-gate devices. Using the proposed framework, one can investigate the implications of WFV for process, device, and circuit design, which are discussed in Part II.

Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation

This work introduces an analytical approach to model the random threshold voltage (Vth) fluctuations in emerging high-k/metal-gate devices caused by the dependency of metal work-function (WF) on its grain orientations. It is shown that such variations can be modeled by a multi-nomial distribution where the key parameters of its probability distribution function (pdf) can be calculated in terms of the physical dimensions of the devices and properties of the materials. It is highlighted for the first time that such variations can have significant implications for the performance and reliability of minimum sized circuits such as SRAM cells.

Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability

This paper investigates the process, device, and circuit design implications of grain-orientation-induced work function variation (WFV) in high-k/metal-gate devices. WFV is caused by the dependence of the work function of metal grains on their orientations and is analytically modeled in the companion paper (part I). Using this modeling framework, various implications of WFV are investigated in this paper. It is shown that process designers can utilize the proposed models to reduce the impact of WFV by identifying proper materials and fabrication processes. For instance, four types of metal nitride gate materials (TiN and TaN for NMOS devices and WN and MoN for PMOS devices) are studied, and it is shown that TiN and WN result in lower V_th fluctuations. Moreover, device engineers can study the impact of WFV on various types of classical and nonclassical metal-gate CMOS transistors using these analytical models. As an example, it is shown that, for a given channel length, single-fin FinFETs are less affected by WFV compared to fully depleted SOI and bulk-Si devices due to their larger gate area. Furthermore, circuit designers can benefit from the proposed modeling framework that allows straightforward evaluation of the key performance and reliability parameters of the circuits under such V_th fluctuations. For instance, an SRAM cell is analyzed in the presence of V_th fluctuations due to WFV, and it is shown that such variations can result in considerable performance and reliability degradation.

Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design

Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This is because to maintain an acceptable noise margin level in deep sub-100 nm technologies, large pMOS keepers must be employed, which generates substantial contention between the keeper and the pull-down network, and hence results in severe loss of performance and high power consumption. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this paper, a novel variation-tolerant keeper architecture is proposed, which is capable of significantly reducing contention and improving performance and power consumption. Using circuit simulations, the overall improved characteristics of the proposed keeper are demonstrated in comparison to those of the traditional as well as several state-of-the-art keepers. The proposed keeper exhibits the lowest delay deviation under different levels of process variations. Also, it is shown that for an eight-input or gate, in presence of 15% Vth fluctuations, the proposed architecture can lead to 20%, 15%, and more than 40% reduction in power consumption, mean delay, and standard deviation of delay, respectively, when compared to the traditional keeper circuit.

A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates

For the first time, a new source of random threshold voltage (Vth) fluctuation in emerging metal-gate transistors is identified, analytically modeled and investigated for its device and circuit-level implications. The new source of variability, christened work-function variation (WFV), is caused by the dependency of metal work-function on the orientation of its grains. A statistical framework is developed, which enables estimation of the key parameters of work-function distribution by identifying the physical dimensions of the devices and properties of materials used in the fabrication. This paper offers three major contributions for process, device and circuit designers. First, the proposed model can be employed to identify suitable materials and fabrication processes that can reduce the impact of Vth fluctuation due to WFV. For instance, four types of metal nitride gate materials (TiN and TaN for NMOS and WN and MoN for PMOS devices) are studied and it is shown that TiN and WN result in lower Vth fluctuation. Second, device engineers can benefit from the result of this work by evaluating the WFV level of various types of classical or non-classical metal-gate CMOS transistors. As an example, it is shown that FinFET transistors are less affected by WFV compared to FD-SOI and bulk-Si devices due to their larger gate area. Third, circuit designers can utilize this model to investigate the impact of such a variation on the key performance and reliability parameters of the circuits. For instance, an SRAM cell is analyzed in the presence of Vth fluctuations due to WFV and it is shown that such variations can result in considerable performance and reliability degradation.

/pdf/statistical-modeling-of-metal-gate-work-function-variability-32w3gvfxrg.pdf

Hamed F. Dadgour

Papers

Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation

Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability

Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design

A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates

Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design