The renewable energy sector and the solar industry, more specifically, are expected to grow in the upcoming years. However, in many colder climates worldwide, ice and snow accumulation on solar panels is prevalent and can negatively affect the efficiency or even stop the production of energy. A superhydrophobic coating has been proposed as a functional coating for use in solar cell and outdoor applications. A review of the literature has revealed that a superhydrophobic coating can be designed to display desirable characteristics that can enhance the efficiency of solar cells and prevent the degradation of efficiency over time. Five properties in relation to superhydrophobic coatings have been discussed: ice resistance, transparency, self-cleaning, antireflection, and mechanical robustness. Included in these discussions were the desired effects of the properties, and the parameters needed to optimize these properties. It was found that the water repellent properties of a superhydrophobic coating can prevent and reduce the accretion of ice, while subsequently the ice resistant properties of the composite wetting state can diminish its adhesion, making ice removal a less energy-intensive process. The good resistance to snow accumulation and the self-cleaning capabilities maintain a clean transparent substrate. Additionally, the transparency and intrinsic antireflective effects can be optimized to ensure maximum light transmission and increased efficiency. A stable and mechanically robust coating would allow for minimal maintenance, prolong the benefits of sought after properties, and increase the overall useful life of a solar panel.

A review of icing prevention in photovoltaic devices by surface engineering

A double-sided and ultrathin 3-D glass interposer with through package vias (TPVs) at same pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs. The 3-D IC stacking approach to achieve high bandwidth has several drawbacks, including the need for TSVs through the logic die, thermal management within the 3-D stack, and the high manufacturing cost associated with wafer-based TSV processing. This paper presents design, fabrication, and electrical characterization of small TPVs (15–40 $\mu{\rm m}$ in diameter) in 30- $\mu{\rm m}$ thin glass to achieve an ultrathin 3-D interposer. This paper also reports the first demonstration of ultrasmall TPVs in glass (15 $\mu{\rm m}$ ) with same dimensions as TSVs in silicon. The signal insertion loss and crosstalk behavior of TPVs in ultrathin glass were investigated and found to be superior to TSVs using 3-D electromagnetic simulations. In demonstrating the 3-D interposers, two process-related challenges were addressed in this paper, namely: 1) defect-free formation of ultrasmall TPV holes with diameters of 15 $\mu{\rm m}$ at 27- $\mu{\rm m}$ pitch and 2) TPV metallization with copper. The fabricated TPVs in ultrathin glass showed a good model to hardware correlation of signal transmission with insertion loss ${ at 20 GHz. The results in this paper suggest that the 3-D interposer concept can be a simpler alternative to 3-D IC stacking with TSVs to achieve high bandwidth between the logic and memory devices.

Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon

Electronic Components and Technology Conference

Fundamentals Of Microsystems Packaging

Carbon Nanotube Arrays with Strong Shear Binding-On and Easy Normal Lifting-Off Liangti Qu, Liming Dai,* Morley Stone, Zhenhai Xia, Zhong Lin Wang* *To whom correspondence should be addressed. E-mail: ldai@udayton.edu (L.D.); zlwang@gatech.edu (Z.L.W.) Published 10 October 2008, Science 322, 238 (2008) DOI: 10.1126/science.1159503 This PDF file includes: Materials and Methods Figs. S1 to S18 References

http://www.nanoscience.gatech.edu/zlwang/paper/2008new/08_cna1.pdf

Supporting Online Material for Carbon Nanotube Arrays with Strong Shear Binding-On and Easy Normal Lifting-Off

This paper presents the latest advances in extending semiadditive process (SAP) methods to 2–5 $\mu \text{m}$ lines and spaces, achieved using dry film photoresists on thin glass substrates, toward meeting the routing requirements for 20- $\mu \text{m}$ bump pitch interposers. High-density chip-to-chip interconnections on 2.5-D interposers are a key enabler to meet the high logic to memory bandwidth needs of next-generation electronic systems. Such 2.5-D interposers require ultrafine redistribution layer (RDL) traces with line widths and spacing below $5~\mu \text{m}$ . This paper reports on the extension of panel scale and lower cost SAPs to achieve less than $5~\mu \text{m}$ lines and spaces, based on the ultrasmooth surface and improved dimensional stability of thin glass panels. A modified low-cost SAP method with newly developed differential seed layer etching was employed to fabricate the fine line and space patterns and coplanar waveguide (CPW) transmission on thin glass panels. Fine lines down to 2- $\mu \text{m}$ lines and spaces and CPW lines with signal lengths up to 5 mm and ground-to-signal gaps down to $5.5~\mu \text{m}$ at 15- $\mu \text{m}$ signal widths were successfully fabricated on ultra-thin glass panels. For comparison, the same processes were also applied to a silicon wafer. The signal insertion losses of CPW lines on the glass were 0.024 dB/mm better at 15 GHz than those on the silicon, as confirmed by simulations as well as VNA measurements. The measured insertion loss of 5-mm long CPW lines on glass interposer was 0.7 dB at 10 GHz and matched well to the simulated values.

Design, Modeling, Fabrication and Characterization of 2–5- $\mu \text{m}$ Redistribution Layer Traces by Advanced Semiadditive Processes on Low-Cost Panel-Based Glass Interposers

Interposer technology is becoming important to interconnect ultra-high performance ICs with ultra-high density I/Os. Silicon interposers fabricated by back-end of line (BEOL) wafer processes address these wiring density requirements, but are limited by their high cost and by their high electrical losses. Organic interposers have limitations too. Their limitations are due to their poor dimensional stability, which require larger capture pads, which limit the I/O density Glass has been proposed by Georgia Tech [1-4] as a superior interposer material to address the limitations of both silicon and organic interposers in recent years. This paper describes the first demonstration of low cost and double sided glass interposer with 3-5 μm line lithography to form multilayer redistribution layers (RDL) to achieve 20 micron bump pitch, ready for chip-level copper interconnections. Unlike prior work using wafer based RDL processes or thin film wiring applied to organic cores, this research applies low cost laminate-like processes, scalable to large panels for lowest cost. To achieve this, semi-additive plating (SAP) process, combined with high resolution dry film photoresists, was optimized to fabricate fine-pitch copper traces with 3-5 μm lines on thin polymer films, laminated on thin glass. Such an ultra-high I/O density of interconnections form the backbone of 2.5D interposers, interconnecting multiple chips. Such ultra-small pitch copper traces can reduce the number of wiring layers required, thus reducing the cost. Compared to sub-micron Cu traces on Si interposers, these 3-5 μm lines are lower in resistance.

Demonstration of 3–5 μm RDL line lithography on panel-based glass interposers

This paper presents the first demonstration of a “zero-undercut” precision formation of ultrafine-line copper conductor patterns for redistribution layers (RDL) and thin film RF passives. This is accomplished by using a highly-anisotropic and uniform copper plasma-etching process to remove the seed layer with no lateral etching of the copper patterns, unlike what is seen with traditional seed-layer removal by wet-etching. Application of this technical breakthrough for large-area panel processes allows demonstration of precision copper patterns demonstrated, for the first time, on organic laminates with no measurable lateral undercut. Two different plasma chemistries, one pure physical sputter-etching, and the other based upon chemical-physical processes with a hydrogen plasma, were investigated and compared.

“zero-undercut” semi-additive copper patterning - a breakthrough for ultrafine-line RDL lithographic structures and precision RF thinfilm passives

This paper describes the first design and fabrication of a large 25D glass interposer with 50 µm pitch chip-level interconnections made of 6 layers of 3 µm re-distribution (RDL) wiring Many applications including high-performance networking and cloud computing data centers require ultra- high-bandwidth of the magnitude of 512 GB/s Silicon-based 25D interposers are the only approaches being pursued by the industry to meet this need, enabled by sub-micron BEOL wiring in the wafer fabs Such interposers, however, are too expensive for most applications Glass interposers are superior to silicon interposers due to their high dimensional stability, low loss tangent, and large panel processing ultimately leading to lower cost This paper presents the design, fabrication and electrical characterization, leading to the first fabrication of 25D glass interposers with 50 µm I/O pitch with 3 µm lines Double-sided panel processing utilizing thin, low-loss dryfilm polymer dielectrics and SAP copper plating, with differential spray etching techniques, was used to fabricate 3 m wide transmission lines on 25mm x 30mm glass interposers processed on a 300 m thick 150mm x 150mm glass panels A six-metal layer test vehicle with two daisy chain, 10mm x 10mm test chips at 100 µm spacing, was fabricated and assembled by thermo-compression bonding of Cu microbumps and SnAg solder caps Ultra-fine 3 µm escape routing was demonstrated on a two-metal layer test vehicle High frequency characterization of 3 µm lines showed low loss of 012 dB/mm at 2 GHz

Modeling, design, fabrication and characterization of first large 2.5D glass interposer as a superior alternative to silicon and organic interposers at 50 micron bump pitch

This paper presents the first demonstration of polycrystalline silicon interposers with fine pitch through package vias (TPV), with less than 5μm RDL lithography at 50μm pitch copper microbump assembly. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. The polycrystalline Si interposer with 100-200μm thick raw Si, obtained without any back-grind or polish, and double side processing, without the use of carriers, has the potential to reduce the cost of wafer-based Si interposers by 2× and up to 10× by scaling to large panels. Thick polymer liner reduces the electrical loss of TPVs dramatically, by an order of magnitude compared to TSVs with SiO2 liner. Initial reliability of TPVs at 150μm and 200μm pitch was demonstrated with daisy chains passing 1000 thermal cycles from -55°C to 125°C. The paper concludes with Cu-SnAg microbump assembly at 50μm pitch onto panel Si interposers with Cu-polymer RDL routing at 4-5μm line lithography.

Hao Lu

Papers

Design, Modeling, Fabrication and Characterization of 2–5- $\mu \text{m}$ Redistribution Layer Traces by Advanced Semiadditive Processes on Low-Cost Panel-Based Glass Interposers

Demonstration of 3–5 μm RDL line lithography on panel-based glass interposers

“zero-undercut” semi-additive copper patterning - a breakthrough for ultrafine-line RDL lithographic structures and precision RF thinfilm passives

Modeling, design, fabrication and characterization of first large 2.5D glass interposer as a superior alternative to silicon and organic interposers at 50 micron bump pitch

Low cost, high performance, and high reliability 2.5D silicon interposer