Y
Yuya Suzuki
Researcher at Georgia Institute of Technology
Publications - 28
Citations - 458
Yuya Suzuki is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Dielectric. The author has an hindex of 10, co-authored 28 publications receiving 397 citations.
Papers
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Journal ArticleDOI
Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon
Vijay Sukumaran,Gokul Kumar,Koushik Ramachandran,Yuya Suzuki,Kaya Demir,Yoichiro Sato,Toshitake Seki,Venky Sundaram,Rao Tummala +8 more
TL;DR: A double-sided and ultrathin 3D glass interposer with through package vias at same pitch as through silicon vias in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs as discussed by the authors.
Proceedings ArticleDOI
Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias
Vijay Sukumaran,Tapobrata Bandyopadhyay,Qiao Chen,Nitesh Kumbhat,Fuhan Liu,R.V. Pucha,Yoichiro Sato,Mitsuru Watanabe,Kenji Kitaoka,Motoshi Ono,Yuya Suzuki,Choukri Karoui,Christian Nopper,Madhavan Swaminathan,Venky Sundaram,Rao Tummala +15 more
TL;DR: In this paper, the authors demonstrate thin glass interposers with fine pitch through package vias (TPV) as a low cost and high I/O substrate for 3D integration.
Proceedings ArticleDOI
Low-cost and low-loss 3D silicon interposer for high bandwidth logic-to-memory interconnections without TSV in the logic IC
TL;DR: In this paper, a low loss and low cost non-traditional silicon interposer is presented, demonstrating the high bandwidth chip-to-chip interconnection capability of the 3D silicon interPOSer, with equivalent or better performance than 3D ICs with TSVs.
Proceedings ArticleDOI
Demonstration of 3–5 μm RDL line lithography on panel-based glass interposers
TL;DR: In this article, a double-sided glass interposer with 3-5 μm line lithography was used to form multilayer redistribution layers (RDL) to achieve 20 micron bump pitch, ready for chiplevel copper interconnections.
Journal ArticleDOI
Design and Demonstration of a 2.5-D Glass Interposer BGA Package for High Bandwidth and Low Cost
Brett Sawyer,Yuya Suzuki,Ryuta Furuya,Chandrasekharan Nair,Ting-Chia Huang,Vanessa Smet,Kadappan Panayappan,Venky Sundaram,Rao Tummala +8 more
TL;DR: In this article, a 2.5D glass interposer is proposed to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers.