National Institute of Standards and Technology における超伝導研究及び生活

http://www.eis.mdx.ac.uk/staffpages/juanaugusto/CookAJ2009.pdf

Review: Ambient intelligence: Technologies, applications, and opportunities

More than a decade of research in the field of thermal, motion, vibration and electromagnetic radiation energy harvesting has yielded increasing power output and smaller embodiments. Power management circuits for rectification and DC-DC conversion are becoming able to efficiently convert the power from these energy harvesters. This paper summarizes recent energy harvesting results and their power management circuits.

Micropower energy harvesting

Wireless sensor network (WSN) technologies are considered one of the key research areas in computer science and the healthcare application industries for improving the quality of life. The purpose of this paper is to provide a snapshot of current developments and future direction of research on wearable and implantable body area network systems for continuous monitoring of patients. This paper explains the important role of body sensor networks in medicine to minimize the need for caregivers and help the chronically ill and elderly people live an independent life, besides providing people with quality care. The paper provides several examples of state of the art technology together with the design considerations like unobtrusiveness, scalability, energy efficiency, security and also provides a comprehensive analysis of the various benefits and drawbacks of these systems. Although offering significant benefits, the field of wearable and implantable body sensor networks still faces major challenges and open research problems which are investigated and covered, along with some proposed solutions, in this paper.

Wearable and Implantable Wireless Sensor Network Solutions for Healthcare Monitoring

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

This paper presents a MUlti-SEnsor biomedical IC (MUSEIC). It features a high-performance, low-power analog front-end (AFE) and fully integrated DSP. The AFE has three biopotential readouts, one bio-impedance readout, and support for general-purpose analog sensors The biopotential readout channels can handle large differential electrode offsets ( ${\pm} $ 400 mV), achieve high input impedance ( ${>}$ 500 M $\Omega$ ), low noise ( ${ 620 nVrms in 150 Hz), and large CMRR ( ${>}$ 110 dB) without relying on trimming while consuming only 31 $\mu$ W/channel. In addition, fully integrated real-time motion artifact reduction, based on simultaneous electrode-tissue impedance measurement, with feedback to the analog domain is supported. The bio-impedance readout with pseudo-sine current generator achieves a resolution of 9.8 m $\Omega$ / $\surd$ Hz while consuming just 58 $\mu$ W/channel. The DSP has a general purpose ARM Cortex M0 processor and an HW accelerator optimized for energy-efficient execution of various biomedical signal processing algorithms achieving 10 $\times$ or more energy savings in vector multiply-accumulate executions.

A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP

In order to simultaneously optimize network lifetime and latency in wireless sensor networks (WSN), an always-on wake-up receiver (WuRx) can be used to monitor the radio link continuously. For truly autonomous sensor nodes employing energy scavenging, only 50µW power is available for the WuRx [1]. An envelope detector is a popular choice in WuRx because of its low power consumption. However, the detector is always the bottleneck of the receiver sensitivity since it attenuates low level input signal and adds excessive noise. One way of improving sensitivity is to amplify the signal before the detector, for example at RF [2, 3] or IF [4] stages, to enhance the SNR at the output.

A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppression

Ultra-low-power (ULP) transceivers enable short-range networks of autonomous sensor nodes for wireless personal-area-network (WPAN) applications. RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ULP WPAN radios. Compared to analog PLLs [1], all-digital PLLs (ADPLLs) are preferred in nanoscale CMOS as they offer benefits of smaller area, programmability, capability of extensive self-calibrations, and easy portability [2]. However, analog PLLs dominate the field of ULP WPAN radios [1], since the time-to-digital-converter (TDC) of an ADPLL has traditionally been power hungry. We present a 2.1-to-2.7GHz 860μW fractional-N ADPLL in 40nm CMOS for WPAN applications, which breaks the 1mW barrier and consumes at least 5× lower power compared to state-of-the-art ADPLLs.

9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications

In the past few years, the use of wireless sensor nodes for remote health care monitoring has been advocated as an attractive alternative to the traditional hospital-centric health care system from both the economic perspective and the patient comfort viewpoint. The semiconductor industry plays a crucial role in making the changes in the health care system a reality. User acceptance of remote health monitoring systems depends on their comfort level, among other factors. The comfort level directly translates to the form factor, which is ultimately defined by the battery size and system power consumption. This article introduces low-power wireless sensor nodes for biomedical applications that are capable of operating autonomously or on very small batteries. In particular, we take a closer look at component-level power optimizations for the radio and the digital signal processing core as well as the trade-off between radio power consumption and on-node processing. We also provide a system-level model for WSNs that helps in guiding the power optimization process with respect to various trade-offs.

Low-power wireless sensor nodes for ubiquitous long-term biomedical signal monitoring

Applications like wireless sensor nodes require ultra low-power receivers with power-efficient ADCs. Moreover, the power-efficiency should be maintained for a wide range of sampling rates to enable system-level flexibility. Previously, the use of SAR ADCs has been proposed for low-power applications [1], [2]. This work describes the implementation of an 8bit asynchronous SAR ADC that achieves a 30fJ/Conversion-step power-efficiency for sampling rates between 10kS/s and 10MS/s.

Harmke de Groot

Papers

A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP

A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppression

9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications

Low-power wireless sensor nodes for ubiquitous long-term biomedical signal monitoring

A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS