The remarkable growth of wireless data traffic in recent times has driven the need to explore suitable regions in the radio spectrum to meet the projected requirements. In pursuance of this, millimeter wave communications have received considerable attention in the research fraternity. Due to the high path and penetration losses at millimeter wavelengths, antenna beamforming assumes a pivotal role in establishing and maintaining a robust communication link. Beamforming for millimeter wave communications poses a multitude of diverse challenges due to the large channel bandwidth, unique channel characteristics, and hardware constraints. In this paper, we track the evolution and advancements in antenna beamforming for millimeter wave communications in the context of the distinct requirements for indoor and outdoor communication scenarios. We expand the scope of discussion by including the developments in radio frequency system design and implementation for millimeter wave beamforming. We explore the suitability of millimeter wave beamforming methods, both, existing and proposed till midyear 2015, and identify the exciting new prospects unfolding in this domain.

Beamforming for Millimeter Wave Communications: An Inclusive Survey

This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (<0.6° rms error) across a ±50° steering range without requiring calibration. A maximum saturated effective isotropic radiated power of 54 dBm is measured in the broadside direction for each polarization. Tapering control without requiring calibration achieves up to 20-dB sidelobe rejection without affecting the main lobe direction.

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications

A 60GHz short-range wireless system offers new opportunities for achieving wireless high-definition video links and multi-Gb/s wireless data transfer. Recent works have realized a 60GHz transceiver by means of a cost-effective CMOS process [1-3], but using a 60GHz system in mobile terminals poses the difficult challenge of achieving low power consumption as well as small form factor. The publication [3] achieves a power consumption of less than 756mW, but uses a simple MAC protocol incompatible with global standards and also suffers from a limited distance of less than 4cm. This paper presents a fully integrated transceiver chipset based on WiGig/IEEE802.11ad standards targeting mobile usage. The chipset is developed for a single-carrier (SC) modulation, which is suitable for reduced power consumption as compared to using OFDM modulation. However, the SC modulation is sensitive to in-band amplitude variation, mainly made worse by the gain variation of analog circuits and multipath delay spread. In order to compensate for those gain variations, the proposed chipset employs built-in TX in-band calibration and an RX frequency domain equalizer (FDE). The proposed techniques can relax the requirement for high speed analog circuits, leading to less power consumption while minimizing the increase of hardware size.

A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications

This work presents a highly integrated 57–64 GHz 4-channel receiver 2-channel transmitter chip targeting short range sensing and large bandwidth communications. The chip is housed in an embedded wafer level ball grid array package. The package includes 6 integrated patch antennas realized with a metal redistribution layer. The receiver patch antennas have a combined antenna gain of $\approx 10$ dBi while each transmitter antenna has a gain of $\approx ~6$ dBi. The chip features a wide tuning range integrated VCO with a measured phase noise lower than −80 dBc/Hz at 100 kHz offset. Each of the differential transmitter channels shows a measured output power of 2–5 dBm over the complete frequency range. In addition, one transmitter channel features a modulator that can be digitally programmed to operate in either radar or communication mode. Each of the receiver channels has a measured conversion gain of 19 dB, a single-sideband noise figure of less than 10 dB and an input referred 1 dB compression point of less than 10 dBm. With all channels turned on the chip consumes a current of 300 mA from a 3.3 V supply. The functionality of the chip is demonstrated for both sensing and short range wireless communications.

A Highly Integrated 60 GHz 6-Channel Transceiver With Antenna in Package for Smart Sensing and Short-Range Communications

This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions. The 65-nm CMOS front-end consumes 319 and 223 mW in transmitting and receiving mode, respectively. It is capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60-GHz standards, which can be extended up to 10 Gb/s. The 40-nm CMOS baseband including analog, digital, and I/O consumes 196 and 427 mW for 16QAM in transmitting and receiving modes, respectively. In the analog baseband, a 5-b 2304-MS/s ADC consumes 12 mW, and a 6-b 3456-MS/s DAC consumes 11 mW. In the digital baseband integrating all PHY functions, a (1440, 1344) LDPC decoder consumes 74 mW with the low energy efficiency of 11.8 pJ/b. The entire system including both RF and BB using a 6-dBi antenna built in the organic package can transmit 3.1 Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

This paper presents a 60GHz direct-conversion front-end and baseband transceiver, including analog and digital circuitry for the PHY functions. The 65nm CMOS front-end consumes 319mW and 223mW in transmitting and receiving mode, respectively, and is capable of more than 7Gb/s 16QAM wireless communication for every channel of the 60GHz standards [1–3]. The 40nm CMOS baseband incorporating LDPC consumes 196mW and 398mW for 16QAM in transmitting and receiving mode, respectively. The entire system, including both RF and BB, using a 6dBi antenna built in an organic package [4] can transmit 3.1Gb/s over 1.8m in QPSK and 6.3Gb/s over 0.05m in 16QAM.

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry

This paper presents low-power, small area analog baseband (ABB) circuits for 60 GHz wireless transceiver in 40 nm CMOS. The ABB circuits consist of 0-to-40 dB VGAs and 5-bit 2304 MS/s flash ADCs for the receiver, and 6-bit 3456 MS/s DACs for the transmitter. The VGAs also work as 2-2-1 order low-pass filters by using negative capacitance generator. The receiver demonstrates SNDR of 27.3 dB at 2304 MS/s with 16 dB VGA gain. The DAC demonstrates SFDR of 40 dB at 3456 MS/s up to 200 MHz. VGAs, ADCs and DACs consume 18 mW, 24 mW and 42 mW from a 1.1 V supply, respectively. The entire ABB circuits occupy an area of 0.36 mm2.

Hironori Sakaguchi

Papers

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry

An 84 mW 0.36 mm 2 analog baseband circuits for 60 GHz wireless transceiver in 40 nm CMOS