H
Hyeok-Ki Hong
Researcher at KAIST
Publications - 12
Citations - 402
Hyeok-Ki Hong is an academic researcher from KAIST. The author has contributed to research in topics: Successive approximation ADC & Effective number of bits. The author has an hindex of 9, co-authored 12 publications receiving 320 citations.
Papers
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Journal ArticleDOI
A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC
TL;DR: The proposed dynamic register and direct DAC control scheme enhance the conversion speed by minimizing logic delay in the SAR decision loop and comparator-error detection with digital error correction scheme enhances high-speed ADC performance.
Journal ArticleDOI
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
Wan Kim,Hyeok-Ki Hong,Yi-Ju Roh,Hyun Wook Kang,Sun-Il Hwang,Dong-Shin Jo,Dong-Jin Chang,Min-Jae Seo,Seung-Tak Ryu +8 more
TL;DR: An asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition is presented and Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty.
Proceedings ArticleDOI
26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique
Hyeok-Ki Hong,Hyun Wook Kang,Dong-Shin Jo,Dong-Suk Lee,Yong-Sang You,Yong-Hee Lee,Ho-Jin Park,Seung-Tak Ryu +7 more
TL;DR: A multi-step hardware-retirement (MSHR) technique, which disables low-accuracy hardware blocks of scaled sizes with the requirement relaxations from redundancies in an advancement to the reconfiguration scheme in the work of Kong et al. (2013), is reported to alleviate the overhead of additional logic and DACs for ADCs, requiring high resolutions.
Proceedings ArticleDOI
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement
Hyeok-Ki Hong,Hyun Wook Kang,Bong-Hyun Sung,Choong-Hoon Lee,Myung-Hoon Choi,Ho-Jin Park,Seung-Tak Ryu +6 more
TL;DR: In this article, a resolution-enhancing design technique for 2b/cycle SAR ADCs with negligible hardware overhead is presented, while relieving the requirements for the aforementioned errors, such as mismatches between DACs and comparators.
Proceedings ArticleDOI
A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control
TL;DR: Use of a nonbinary decision scheme for decision error correction in a 2b/cycle structure not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robust to reference fluctuation and signal-dependent comparator offset variation.