A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

TLDR: An asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition is presented and Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty.

Abstract: This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-but-low-quality clock for low-frequency operation. With the dual-mode clock generator enabled, a prototype 65 nm CMOS 0.6 V 12 b 10 MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24 LSB and 0.45 LSB, respectively. The FoM is 6.2 fJ/conversion-step with a power consumption of $83~\mu \text {W}$ . The ADC operates under the lowest supply voltage of 0.6 V among comparable designs with ENOBs over 10 and conversion rates over 1 MS/s.