This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) that is much smaller and faster than other recently reported precision (16-bit and beyond) SAR ADCs. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference using reservoir capacitors to improve speed and reduce area, plus LSB repeats and statistical residue measurement to improve efficiency. The prototype achieves 97.5-dB spurious-free dynamic range at 100-kHz input while operating at 16 MS/s and consumes 16.3 mW. It was fabricated in a 55-nm CMOS process and occupies 0.55 mm2.

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

An asynchronous successive approximation register analog-to-digital converter (ADC) for wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s 10-b, 40-MS/s 11-b, or 20-MS/s 12-b converter. Time-interleaved technique is applied to expand sampling bandwidth exponentially while resolution scales down. The channel mismatches are cancelled by the digital calibration technique. The bulk-biasing technique is used in the sampling switch to reduce the influence of the charge injection caused by the top-plate sampling. In addition, the configurable asynchronous processing is employed to extend the flexibility of speed and resolution tradeoff. Moreover, the two-step digital-to-analog converter (DAC) switching method is proposed to reduce the switching energy of the DAC. Prototyped in 180-nm CMOS process, the ADC achieves the 56.7-/61.2-/64.6-dB signal-to-noise and distortion ratio (SNDR) and 72.3-/74.8-/75.5-dB spurious-free dynamic range (SFDR) at 80-/40-/20-MHz sampling frequency with the power consumption of 2.61/2.05/1.77 mW.

A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC

Integrated recording of neural electrical potentials from the brain poses great challenges due to stringent dynamic range requirements to resolve small-signal amplitudes buried in noise amidst large artifact and stimulation transients, as well as stringent power and volume constraints to enable minimally invasive untethered operation. Here, we present a 16-channel neural recording system-on-chip with greater than 90-dB input dynamic range and less than 1- $\mu \text{V}_{\mathrm {rms}}$ input-referred noise from dc to 500 Hz, at 0.8- $\mu \text{W}$ power consumption, and 0.024-mm2 area per channel in a 65-nm CMOS process. Each recording channel features a hybrid analog–digital second-order oversampling analog-to-digital converter (ADC), with the biopotential signal coupling directly to the second integrator for high conversion gain and dynamic offset subtraction in the digital domain. This bypasses the need for high-pass filtering pre-amplification in neural recording systems, which often leads to signal distortion. The integrated ADC-direct neural recording offers record figure-of-merit with a noise efficiency factor (NEF) of the combined front end and ADC of 1.81, and a corresponding power efficiency factor (PEF) of 2.6. Predictive digital autoranging of the binary quantizer further supports rapid transient recovery while maintaining fully dc-coupled operation. Hence, the neural ADC is capable of recording ${\le}$ 0.01-Hz slow potentials as well as recovering from $\ge$ 200-mVpp transients within ${\le}$ 1 ms that are important prerequisites to effective electrocortical recording for brain activity mapping. In vivo recordings from marmoset primate frontal cortex demonstrate its unique capabilities in resolving ultra-slow local field potentials indicative of subject arousal state.

/pdf/sub-mu-v-rms-noise-sub-mu-w-channel-adc-direct-neural-4gtsanecqq.pdf

Sub- $\mu$ V rms -Noise Sub- $\mu$ W/Channel ADC-Direct Neural Recording With 200-mV/ms Transient Recovery Through Predictive Digital Autoranging

We present multiscatter, a novel backscatter design that can simultaneously work with multiple excitation signals for personal IoT sensors. Specifically, we show for the first time that the backscatter tag can identify various excitation signals in an ultra-low-power way, including WiFi, Bluetooth, and ZigBee. Further, we employ a new modulation approach, overlay modulation, that can leverage those excitation signals to convey tag data on top of productive data, which makes decoding both data possible with only a single personal radio. Since 2.4 GHz signals and personal radios are everywhere, multiscatter is readily deployable in our everyday IoT applications. We prototype multiscatter using an FPGA and various commodity radios. Extensive experiments show that for mixed 802.11b&n, Bluetooth and ZigBee signals, the average identification accuracy of four protocols is more than 93%. The maximal aggregate throughput of both productive and tag data is 278.4 kbps with a single Bluetooth radio, and the maximal backscatter ranges are 28 m, 22 m, and 20 m for WiFi, Bluetooth, and ZigBee, respectively. We also demonstrate that it can leverage excitation diversity to provide uninterrupted communication and greater throughput gains, whereas the single-protocol tag being idle when target carriers are not available.

Multiprotocol backscatter for personal IoT sensors

A temperature-stabilized 12-bit single-channel successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC) running at 1 GS/s with Nyquist signal to noise and distortion ratio (SNDR) above 60 dB is presented. The ADC uses a three-stage (4 b-4 b-6 b) SAR-assisted pipeline hybrid architecture to achieve an attractive energy efficiency along with an extended sampling rate. A high-linearity open-loop Gm-R-based residue amplifier (RA) with both complete-settled and dynamic features improves the residue amplification efficiency and speed, while reducing the gain variation over a temperature drift. The inter-stage gain variation over the temperature is compensated through complementary temperature coefficients (TCs) from the inner devices of the RA. Furthermore, a cascade amplification topology in the backend RA alleviates the effect of the input parasitic capacitance to its front-end capacitor DAC (CDAC), thus leading to a small CDAC size to accelerate amplification and conversion. The prototype ADC was fabricated in a 28-nm CMOS process and consumes 7.6 mW from a 1-V power supply at 1 GS/s. The measured inter-stage gain variation is less than 2.3% with a temperature range from 0 °C to 80 °C. The SNDR and SFDR are 60 and 74.6 dB with a Nyquist input, respectively, achieving a Walden figure-of-merit (FoM) of 9.3 fJ/conversion-step and a Schreier FoM of 168.2 dB.

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier

This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-but-low-quality clock for low-frequency operation. With the dual-mode clock generator enabled, a prototype 65 nm CMOS 0.6 V 12 b 10 MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24 LSB and 0.45 LSB, respectively. The FoM is 6.2 fJ/conversion-step with a power consumption of $83~\mu \text {W}$ . The ADC operates under the lowest supply voltage of 0.6 V among comparable designs with ENOBs over 10 and conversion rates over 1 MS/s.

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the image properties. The proposed delta-readout ( $\Delta $ -readout) scheme reads the signal difference between two pixels located next to each other ( $\Delta _{\mathrm {pixel}}$ ) by utilizing the most significant bits (MSBs) information of the previous pixel. By effectively reducing the dynamic range of the signal, compensated by the $\Delta $ -window checking, the proposed $\Delta $ -readout scheme can reduce the effective number of decision cycles in a successive-approximation register (SAR) analog-to-digital converter (ADC) and reduce the power consumption while preserving the ADC performance. A prototype QQVGA CIS with ten 10-bit SAR ADCs in a multi-column-parallel (MCP) configuration was fabricated in a $0.18~\mu \text {m}~1$ P4M CIS process with a $4.4~\mu \text {m}$ pixel pitch, where each single ADC occupies an area of $70\,\,\mu \text {m}\,\,\times \,\,500\,\,\mu \text {m}$ . The measurement results of the implemented prototype CIS showed a maximum power-saving of 26% with a figure-of-merit (FoM) for ADC of 15 fJ/conversion-step.

A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs

This paper presents a CMOS image sensor (CIS) utilizing a noise-shaping successive-approximation register analog-to-digital converter (SAR ADC) incorporating the delta-readout scheme. While the noise-shaping SAR ADC with a proposed two-tap passive finite-impulse response (FIR) filter improves effective resolution, the delta-readout scheme reduces its power consumption. A prototype $1920\times 1440$ pixel CIS was fabricated in a 90-nm CIS process. A single-channel readout SAR ADC occupying an area of ${22.4}\,\,\mu \textsf {m}\times {715}\,\,\mu \text{m}$ was implemented for reading out 16 columns of pixel array, consuming $437~\mu \text{W}$ . Owing to the proposed noise-shaping SAR ADC with oversampling ratio of 16, this paper achieves a noise reduction of 14 dB compared with the noise of a conventional SAR ADC. The delta-readout reduces the power consumption of the SAR ADC by 10% due to the high hit rate of the full high definition image format. The measured differential nonlinearity of the ADC is +0.77/ −0.54 LSB and the integral nonlinearity is +0.81/ −0.5 LSB. The prototype CIS consumes a total power of 64 mW and achieves a dynamic range of 66.5 dB and a figure of merit of $127~\mu \text{V}\cdot $ nJ at a data rate of 138 Mpixels/s.

A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs

This paper presents a CMOS image sensor (CIS) that extracts a multi-level edge image as well as a human-friendly normal image in a real time from conventional pixels for machine-vision applications, utilizing a proposed speed/power-efficient dual-mode successive-approximation register analog-to-digital converter (SAR ADC). The proposed readout scheme operates in two modes, fine step SAR (FS-SAR) mode and coarse-step single-slope (CS-SS) mode, depending on the difference ( $\Delta $ ) between a chosen pixel and the previous pixel. If a chosen pixel is at a boundary of an object with a large $\Delta $ from the previous pixel, the readout ADC works in the CS-SS mode to readout the edge strength (ES), while the FS-SAR mode is applied for other pixels. By displaying the ES, a multi-level edge image can be obtained in a real time along with a normal image with no hardware/time overhead. By saving the MSBs conversion cycles regardless of $\Delta $ , the proposed dual-mode readout scheme enhances the readout speed and reduces power consumption. A prototype QQVGA CIS with 10-bit SAR ADCs was fabricated in a 0.18- $\mu \text{m}$ 1P4M CMOS image sensor process with a 4.9- $\mu \text{m}$ pixel pitch. With a maximum pixel rate of 61.4 Mp/s, the prototype demonstrated figure of merits of 70 pJ/pixel/frame, 0.35 $\text{e}^{-}\cdot \text {nJ}$ , and 0.34 $\text{e}^{-}\cdot \text {pJ}$ /step.

A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction

This paper proposes a low-power logarithmic resistance sensor for multi-level cell phase-change memory readout The proposed sensor is composed of a resistance-to-current converter (R2I) and a current-to-digital converter (I2D) A simple bleeding current source pair added to the R2I enhances the current settling speed and the sensing accuracy The two-step I2D with a time-to-digital converter-configured fine ADC could be designed with low-power consumption and small size owing to the time-reference generator that is shared by multiple channels and incorporates interpolation and size-scaling techniques The total conversion time of the readout sensor, including the R2I conversion, is 100 ns, and the power consumption of a single-channel readout sensor is 60 μW under a 12 V supply The ratio of the minimum decision step size to the full scale input current of the I2D corresponds to that of a conventional 96-b linear ADC The prototype sensor is composed of 14-channels sharing a single time-reference generator, where each narrow single channel occupies 19 μm × 590 μm in a 65-nm CMOS process

Sun-Il Hwang

Papers

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs

A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs

A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction

A Low-Power TDC-Configured Logarithmic Resistance Sensor for MLC PCM Readout