This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) that is much smaller and faster than other recently reported precision (16-bit and beyond) SAR ADCs. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference using reservoir capacitors to improve speed and reduce area, plus LSB repeats and statistical residue measurement to improve efficiency. The prototype achieves 97.5-dB spurious-free dynamic range at 100-kHz input while operating at 16 MS/s and consumes 16.3 mW. It was fabricated in a 55-nm CMOS process and occupies 0.55 mm2.

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

An asynchronous successive approximation register analog-to-digital converter (ADC) for wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s 10-b, 40-MS/s 11-b, or 20-MS/s 12-b converter. Time-interleaved technique is applied to expand sampling bandwidth exponentially while resolution scales down. The channel mismatches are cancelled by the digital calibration technique. The bulk-biasing technique is used in the sampling switch to reduce the influence of the charge injection caused by the top-plate sampling. In addition, the configurable asynchronous processing is employed to extend the flexibility of speed and resolution tradeoff. Moreover, the two-step digital-to-analog converter (DAC) switching method is proposed to reduce the switching energy of the DAC. Prototyped in 180-nm CMOS process, the ADC achieves the 56.7-/61.2-/64.6-dB signal-to-noise and distortion ratio (SNDR) and 72.3-/74.8-/75.5-dB spurious-free dynamic range (SFDR) at 80-/40-/20-MHz sampling frequency with the power consumption of 2.61/2.05/1.77 mW.

A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC

A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed.

Re-Thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

Integrated recording of neural electrical potentials from the brain poses great challenges due to stringent dynamic range requirements to resolve small-signal amplitudes buried in noise amidst large artifact and stimulation transients, as well as stringent power and volume constraints to enable minimally invasive untethered operation. Here, we present a 16-channel neural recording system-on-chip with greater than 90-dB input dynamic range and less than 1- $\mu \text{V}_{\mathrm {rms}}$ input-referred noise from dc to 500 Hz, at 0.8- $\mu \text{W}$ power consumption, and 0.024-mm2 area per channel in a 65-nm CMOS process. Each recording channel features a hybrid analog–digital second-order oversampling analog-to-digital converter (ADC), with the biopotential signal coupling directly to the second integrator for high conversion gain and dynamic offset subtraction in the digital domain. This bypasses the need for high-pass filtering pre-amplification in neural recording systems, which often leads to signal distortion. The integrated ADC-direct neural recording offers record figure-of-merit with a noise efficiency factor (NEF) of the combined front end and ADC of 1.81, and a corresponding power efficiency factor (PEF) of 2.6. Predictive digital autoranging of the binary quantizer further supports rapid transient recovery while maintaining fully dc-coupled operation. Hence, the neural ADC is capable of recording ${\le}$ 0.01-Hz slow potentials as well as recovering from $\ge$ 200-mVpp transients within ${\le}$ 1 ms that are important prerequisites to effective electrocortical recording for brain activity mapping. In vivo recordings from marmoset primate frontal cortex demonstrate its unique capabilities in resolving ultra-slow local field potentials indicative of subject arousal state.

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Sub- $\mu$ V rms -Noise Sub- $\mu$ W/Channel ADC-Direct Neural Recording With 200-mV/ms Transient Recovery Through Predictive Digital Autoranging

We present multiscatter, a novel backscatter design that can simultaneously work with multiple excitation signals for personal IoT sensors. Specifically, we show for the first time that the backscatter tag can identify various excitation signals in an ultra-low-power way, including WiFi, Bluetooth, and ZigBee. Further, we employ a new modulation approach, overlay modulation, that can leverage those excitation signals to convey tag data on top of productive data, which makes decoding both data possible with only a single personal radio. Since 2.4 GHz signals and personal radios are everywhere, multiscatter is readily deployable in our everyday IoT applications. We prototype multiscatter using an FPGA and various commodity radios. Extensive experiments show that for mixed 802.11b&n, Bluetooth and ZigBee signals, the average identification accuracy of four protocols is more than 93%. The maximal aggregate throughput of both productive and tag data is 278.4 kbps with a single Bluetooth radio, and the maximal backscatter ranges are 28 m, 22 m, and 20 m for WiFi, Bluetooth, and ZigBee, respectively. We also demonstrate that it can leverage excitation diversity to provide uninterrupted communication and greater throughput gains, whereas the single-protocol tag being idle when target carriers are not available.

Multiprotocol backscatter for personal IoT sensors

This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-but-low-quality clock for low-frequency operation. With the dual-mode clock generator enabled, a prototype 65 nm CMOS 0.6 V 12 b 10 MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24 LSB and 0.45 LSB, respectively. The FoM is 6.2 fJ/conversion-step with a power consumption of $83~\mu \text {W}$ . The ADC operates under the lowest supply voltage of 0.6 V among comparable designs with ENOBs over 10 and conversion rates over 1 MS/s.

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

This brief proposes a code-reusable design methodology for synthesizable successive approximation register (SAR) ADCs based on the digital design flow to significantly reduce design effort. The SAR ADCs are composed of a capacitor-DAC (CDAC) macro cell generated by a CDAC compiler and analog functional blocks implemented utilizing digital standard cells. Two prototypes of SAR ADCs (12-bit 100 kS/s and 11-bit 50 MS/s) are fabricated in different CMOS processes (180 nm and 28 nm). The prototype ADCs prove the effectiveness of the proposed design methodology with comparable performances with full-custom designed SAR ADCs.

A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks

A SAR-assisted SAR ADC that uses a double clock-rate coarse decision technique is presented. The coarse ADC operates with a higher rate clock to reduce the MSBs decision time. The mismatch problem between coarse and fine ADCs is solved by using redundancy and background offset calibration. A simple metastability reduction technique for non-binary SAR ADC that does not require a lookup table is also proposed. The ADC core occupies a 0.0128-mm2 area and consumes 1.9 mW under a 1-V supply. With an 80-MHz input, the ADC achieves an SNDR of 58.1 dB and an SFDR of 72.1 dB. The peak DNL and INL are 0.96 LSB and 1.6 LSB, respectively, and the figure of merit is 24.26 fJ/conversion-step.

A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision

This paper presents a four-channel time-interleaved high-speed current-steering DAC with a proposed two-stage analog multiplexer (MUX). Optimum switching times of the cascaded MUX and the sub-DACs are guaranteed by background clock phase calibration with a proposed maximum-overlap-based phase detector. A 6b 28GS/s prototype DAC fabricated in 40nm CMOS achieves a SFDR of 34.6dB at a Nyquist input and consumes 103mW under dual supply voltages of 1.1V and 1.6V.

A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration

The present disclosure provides an electronic circuit including a reference analog-to-digital converter (ADC) and sub ADCs. The reference ADC converts an input signal into reference data in response to a reference clock. The plurality of sub ADCs respectively converts input signals into a plurality of output data in response to a plurality of conversion clocks providing different timings. Based on output data corresponding to a difference of the difference between the reference data and each of the plurality of output data, and the plurality of output data, a timing of a conversion clock associated with the output data corresponding to the difference among the plurality of conversion clocks is adjusted. According to embodiments of the present invention, timing errors of a plurality of clocks, which are time-interleaving, may be eliminated.

Yi-Ju Roh

Papers

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks

A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision

A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration

Electronic circuit adjusting skew between plurality of clocks based on derivative of input signal