H
Hyungdong Lee
Researcher at SK Hynix
Publications - 62
Citations - 1453
Hyungdong Lee is an academic researcher from SK Hynix. The author has contributed to research in topics: Through-silicon via & Three-dimensional integrated circuit. The author has an hindex of 16, co-authored 62 publications receiving 1329 citations. Previous affiliations of Hyungdong Lee include KAIST.
Papers
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Journal ArticleDOI
High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)
Joohee Kim,Jun So Pak,Jonghyun Cho,Eakhwan Song,Jeonghyeon Cho,Heegon Kim,Taigon Song,Jun Ho Lee,Hyungdong Lee,Kunwoo Park,Seung-Taek Yang,Min Suk Suh,Kwang-Yoo Byun,Joungho Kim +13 more
TL;DR: In this article, the authors proposed a high-frequency scalable electrical model of a through silicon via (TSV) channel, which includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3D integrated circuit (IC) design.
Journal ArticleDOI
Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring
Jonghyun Cho,Eakhwan Song,Kihyun Yoon,Jun So Pak,Joohee Kim,Woojin Lee,Taigon Song,Kiyeong Kim,Jun Ho Lee,Hyungdong Lee,Kunwoo Park,Seung-Taek Yang,Min Suk Suh,Kwang-Yoo Byun,Joungho Kim +14 more
TL;DR: In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM) and a noise isolation technique using a guard ring structure is proposed.
Journal ArticleDOI
PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models
Jun So Pak,Joohee Kim,Jonghyun Cho,Kiyeong Kim,Taigon Song,Seungyoung Ahn,Jun Ho Lee,Hyungdong Lee,Kunwoo Park,Joungho Kim +9 more
TL;DR: In this article, a power/ground (P/G) TSV array model based on separated P/G TSV and chip-PDN models at frequencies up to 20 GHz is proposed for estimating the PDN impedances of 3D TSV ICs.
Proceedings ArticleDOI
Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer
Kihyun Yoon,Gawon Kim,Woojin Lee,Taigon Song,Jun Ho Lee,Hyungdong Lee,Kunwoo Park,Joungho Kim +7 more
TL;DR: In this article, a lumped element model for coupled interconnect structures of TSV, metal interconnects, and Redistribution Layer (RDL) in 3D IC with silicon interposer is presented.
Proceedings ArticleDOI
Active circuit to through silicon via (TSV) noise coupling
Jonghyun Cho,Jongjoo Shim,Eakhwan Song,Jun So Pak,Jun Ho Lee,Hyungdong Lee,Kunwoo Park,Joungho Kim +7 more
TL;DR: In this paper, a 3D-TLM-based coupling model between through silicon via (TSV) and substrate based on a 3-dimensional transmission line matrix (3DTLM), which utilizes equivalent lumped circuit model of silicon substrate and TSV was proposed.