Polar or outphasing radio transmitter architectures promise higher efficiency than their Cartesian counterparts [1], but require the adoption of phase modulators with bandwidth about one order of magnitude wider than the channel bandwidth. In contrast to phase-switching approaches [2], efficient implementations of wideband phase modulators are based on the direct frequency modulation (FM) of a PLL and on the two-point signal-injection scheme [3]. Unfortunately, meeting the noise/bandwidth requirements of 4G wireless standards (such as WiMAX) demands fine frequency resolution, tight VCO linearity and accurate synchronization between the two signals injected into the PLL. This paper introduces a digital-intensive phase modulator circuit, which is able to enforce an arbitrary carrier phase change (up to ±π radians) in one clock sample. For a clock frequency of 40MHz, the modulation error, expressed in terms of error vector magnitude (EVM), is below −36dB for a 20Mb/s QPSK-modulated or a 10Mb/s GMSK-modulated carrier at 3.6GHz.

A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With −36 dB EVM at 5 mW Power

The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL that has resulted in an all-digital frequency synthesizer with the best-in-class RF performance while occupying only a fraction of the silicon area and consuming a fraction of the power. The paper also offers a few novel techniques to further improve area, current consumption, testability, and reliability of frequency synthesizers.

State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS

We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm2 and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS

Charge-Pump Phase-Locked Loops에 관한 연구 및 회로 설계

A polar modulator for wireless RF transmitters nonlinearly transforms complex-valued Cartesian baseband modulating signal into amplitude and phase components of the polar coordinate representation before they are recombined in a power amplifier. The resulting explosion in the bandwidth requirements of the polar components can so far be only tolerated for narrowband transmitters, such as EDGE of the 2G cellular. To enable polar topology for wideband transmitters, we propose a technique that alters the signal trajectory such that it avoids crossing (and proximity) of the constellation origin. The resulting substantial decrease of the polar modulator bandwidth is traded off against slight increase of in-band modulation distortion and adjacent channel leakage. We illustrate effectiveness of this method using wideband CDMA (WCDMA) of the 3G cellular. The technique is first mathematically analyzed for various tradeoffs followed by high-level modeling and simulation results. Since the technique is fully contained in the digital domain, its performance effects on the entire RF transmitter can be accurately simulated. A digital architecture to implement the proposed technique is also presented.

A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter

A new phase-domain all-digital phase-locked loop (ADPLL) for RF wireless applications has recently been proposed and commercially demonstrated. In this brief, we propose time-domain modeling and simulation techniques of the ADPLL that are well suited for system analysis using high-level programming languages, e.g., Matlab. They are based on the event-driven principles inherent in hardware description languages, e.g., VHDL, and enable the development of accurate and time-efficient behavioral models. The proposed techniques are demonstrated and validated through experimental results for a GSM standard.

Time-Domain Modeling of an RF All-Digital PLL

We investigate the recombination of discrete-time envelope and phase/frequency components of a polar transmitter, which is based here on an all-digital phase-locked loop (ADPLL) with wideband modulation capability and a digitally controlled power amplifier (DPA). A unified discrete/continuous-time analysis is introduced for the development of the interpolative transfer characteristics of the envelope and phase paths that allows their recombination to be studied in the continuous-time domain of the DPA radio-frequency output. The nonlinear recombination of the polar components in the DPA is analytically investigated in the context of a proposed characterization technique that utilizes single-tone envelope and phase signals, and conclusions on the optimal architecture of a wideband ADPLL-based polar transmitter are drawn. The harmonic distortion results obtained in the context of the proposed characterization technique effectively highlight the performance of the polar transmitter when it is driven with the wideband baseband envelope and phase-modulating signals of today's high-data-rate digital communication systems, such as wideband code-division multiple access and beyond.

Recombination of Envelope and Phase Paths in Wideband Polar Transmitters

All-digital phase-locked loops (ADPLL) are inherently multirate systems with time-varying behavior. In support of this statement linear time-variant (LTV) models of ADPLL are presented that capture spectral aliasing effects that are not captured by linear time-invariant (LTI) models. It is analytically shown that the latter are subset of the former. The high-speed ΣΔ modulator that improves the frequency resolution of the digitally-controlled oscillator (DCO) is included, too. It realizes fractional resampling and interpolation of the tuning data of the DCO. The noise transfer from all three operating clock domains of the ADPLL (reference, ΣΔ, and DCO) to its output phase is accurately predicted and design metrics are derived with regard to its folded close-in and far-out phase noise performance. The analytical results are validated via simulations using measured event-driven modeling techniques for a CMOS RF ADPLL.

Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops

A new all-digital phase-locked loop (ADPLL) for wireless applications has recently been proposed and commercially demonstrated. It replaces conventional phase/frequency detector and charge pump with a time-to-digital converter (TDC). Analog frequency tuning of a VCO is replaced with an all- digital tuning of a digitally-controlled oscillator (DCO). Due to its digital intensive structure, the ADPLL is well suited for single-chip radio solutions fabricated using state-of-the- art low cost and power nanometer-scale CMOS processes. Being integrated with a digital signal processor (DSP), the ADPLL parameters can be properly controlled and seamlessly reconfigured using the available on-chip DSP unit making the ADPLL a software defined radio (SDR) platform. In this paper, we present a DSP based technique for the fully dynamic control of the ADPLL settling performance that allows the loop band width to be seamlessly widened or narrowed allowing for fast frequency acquisition or tracking with excellent phase noise and spurious performance, respectively. The arbitrary and dynamic control of the frequency synthesizer loop bandwidth will address the dynamically varying nature of a multi-radio multi- standard SDR environment.

On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios

A new all-digital phase-locked loop (ADPLL) for RF wireless applications has recently been proposed and commercially demonstrated. It replaces conventional phase/frequency detector and charge pump with a time-to-digital converter (TDC). Analog frequency tuning of a VCO is replaced with an all-digital tuning of a digitally-controlled oscillator (DCO). In this paper, we present novel time-domain modeling and simulation techniques of the ADPLL phase detection mechanism as well as the frequency perturbation and phase noise characteristics of the DCO. The modeling principles are demonstrated for a GSM standard and validated through experimental results.

I.L. Syllaios

Papers

Time-Domain Modeling of an RF All-Digital PLL

Recombination of Envelope and Phase Paths in Wideband Polar Transmitters

Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops

On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios

Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications