An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock. The measured fractional spur is less than −64 dBc across the 5.5–7.3-GHz output frequency band. The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur. This design meets the performance requirement of the 5G cellular 64-quadratic-amplitude modulation (QAM) standard in the 28-/39-GHz band, supporting $2 \times 2$ multi-in multi-out (MIMO). This paper, implemented in a 28-nm CMOS process, is integrated in a 5G millimeter-wave cellular transceiver. This PLL consumes 18.9 mW and occupies 0.45 mm2.

A 28-nm 75-fs rms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

This paper presents a sub-mW fractional- ${N}$ all-digital phase-locked loop (ADPLL) with scalable power consumption, which achieves an figure of merit (FOM) of −246 dB. The proposed 10-b ultralow-power isolated constant-slope digital-to-time converter (DTC) achieves a 580-fs resolution and a measured integral nonlinearity (INL) of 870 fs with 0.14-mW power consumption at 52 MS/s. A narrow-range time amplifier (TA)-time-to-digital converter (TDC) with gain calibration minimizes both the in-band phase noise degradation and the loop-bandwidth variation. In addition, a coarse-DPLL is introduced with dead-zone function, which reduces the phase lock time to 4.2 $\mu \text{s}$ at a 13-MHz frequency error. The coarse-DPLL monitors large frequency and phase jump in the background while consuming almost zero power. In an ultralow power mode, the proposed fractional- ${N}$ ADPLL consumes a 0.65-mW power with a 26-MHz reference. A rms jitter of 1.00 ps and −50-dBc in-band fractional spur are achieved with a −242-dB FOM. In high-performance mode, a reference doubler is utilized, the jitter and spurs can be improved to 535 fs and −56 dBc, respectively, while consuming 0.98 mW. The proposed ADPLL with scalable power and jitter performance can be utilized for Internet-of-Things (IoT) applications, such as Bluetooth low energy (BLE) and Wi-Fi networks.

/pdf/a-sub-mw-fractional-n-adpll-with-fom-of-246-db-for-iot-134skdrnel.pdf

A Sub-mW Fractional- ${N}$ ADPLL With FOM of −246 dB for IoT Applications

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS

Precision oscillators are ubiquitous in modern electronic systems, and their accuracy often limits the performance of such systems Hence, a deep understanding of how oscillator performance is quantified, simulated, and measured, and how it affects the system performance is essential for designers Unfortunately, the necessary information is spread thinly across the published literature and textbooks with widely varying notations and some critical disconnects This paper addresses this problem by presenting a comprehensive one-stop explanation of how oscillator error is quantified, simulated, and measured in practice, and the effects of oscillator error in typical oscillator applications

https://ieeexplore.ieee.org/ielaam/8919/8566198/8449324-aam.pdf

Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement

Direct-RF data converters [1,2] have seen increased adoption in remote-radio-head TX and RX, due to their unparalleled bandwidth and flexibility. However, since these converters need to directly synthesize and sample multi-GHz radio signals, the sampling clock must exhibit excellent phase-noise performance, to minimize self- and adjacent-channel mixing, and strong suppression of reference and harmonic spurs, to meet stringent out-of-band emissions and minimize aliased energy. Furthermore, a wide range of sampling frequencies is required for the flexibility to cover multiple bands. Due to these stringent requirements, typically, external PLLs are employed, adding to the BOM cost. This work presents techniques for a fully integrated 7.4-to-14GHz PLL in 16nm FinFET that has 54fs rms jitter to satisfy the low noise requirements of RF data converters.

A 7.4-to-14GHz PLL with 54fs rms jitter in 16nm FinFET for integrated RF-data-converter SoCs

A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137- and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a frequency multiplication ratio of 207.0019231 [digitally controlled oscillator (DCO) frequency is 50 kHz away from an integer multiple of the 26-MHz reference clock], a −78.6-dBc fractional spur is achieved for an output clock that runs at half of the DCO frequency. Time-to-digital converter (TDC) chopping technique, TDC fine conversion through successive approximation register analog-to-digital converters (SARADCs), and TDC nonlinearity calibration improve integrated phase noise and fractional spurs. This design meets the performance requirement of the 256-QAM $4 \times 4$ MIMO LTE standard in 5-GHz ISM band and also the 5G cellular 64-QAM standard in 28-GHz band. This work, implemented in a 14-nm fin-shaped field effect transistor (FinFET) CMOS process, is integrated to a cellular RF integrated circuit supporting advanced carrier aggregation operation. This PLL draws 13.4 mW and occupies 0.257 mm2.

A 14-nm 0.14-ps rms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

To meet ever-growing demands for higher mobile data-rates, LTE standards continue to evolve. While carrier aggregation (CA) improves data-rates, it requires wider aggregated signal bandwidth that limits the number of users that can be serviced. Techniques like 256QAM and 4×4 MIMO are attractive because improvements do not need wider signal bandwidth. To support 256QAM and 4×4 MIMO for the 5GHz band, we need IPN better than −48dBc or 155fsec rms. A digital fractional-N PLL that achieves 137fsec rms jitter integrating from 10kHz to 10MHz (or 142fsec 1kHz to 10 MHz) with a −78.6dBc near integer-N fractional spur is presented. We have introduced a TDC chopping technique, fine-conversion through SARADCs and TDC nonlinearity calibration to improve IPN and fractional spurs.

24.8 A 14nm fractional-N digital PLL with 0.14ps rms jitter and −78dBc fractional spur for cellular RFICs

The proposed fully-integrated digital-intensive TRX SoC allows dual-mode protocols of BLE 5.0 and IEEE 802.14.5 with extended-range wireless connectivity and simple ad-hoc mesh networks for the IoTs in smart homes. A 1.04 - 4V with dual-mode supply schemes enables the SoC to be applied for various IoT systems energy-effectively and extends battery lifetime cost-effectively. The TRX employs a low insertion loss CMOS transmit- receive switch, a class-D power amplifier with HD2 calibration, a low-IF RX architecture with ΔΣ ADC-based complex filter, and a low power ADPLL with LMS-based two-point direct frequency modulation. The TRX implemented in a 28nm CMOS process achieves the maximum output power of +10dBm while consuming 45mW at the TX, <-102dBm at IEEE802.15.4 mode while consuming 6mW at the RX.

Ikkyun Jo

Papers

A 14-nm 0.14-ps rms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

24.8 A 14nm fractional-N digital PLL with 0.14ps rms jitter and −78dBc fractional spur for cellular RFICs

A 1.04 - 4V, Digital-Intensive Dual-Mode BLE 5.0/IEEE 802.15.4 Transceiver SoC with extended range in 28nm CMOS