An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock. The measured fractional spur is less than −64 dBc across the 5.5–7.3-GHz output frequency band. The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur. This design meets the performance requirement of the 5G cellular 64-quadratic-amplitude modulation (QAM) standard in the 28-/39-GHz band, supporting $2 \times 2$ multi-in multi-out (MIMO). This paper, implemented in a 28-nm CMOS process, is integrated in a 5G millimeter-wave cellular transceiver. This PLL consumes 18.9 mW and occupies 0.45 mm2.

A 28-nm 75-fs rms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

Low jitter large frequency tuning LC PLL for multi-speed clocking applications

This paper presents a sub-mW fractional- ${N}$ all-digital phase-locked loop (ADPLL) with scalable power consumption, which achieves an figure of merit (FOM) of −246 dB. The proposed 10-b ultralow-power isolated constant-slope digital-to-time converter (DTC) achieves a 580-fs resolution and a measured integral nonlinearity (INL) of 870 fs with 0.14-mW power consumption at 52 MS/s. A narrow-range time amplifier (TA)-time-to-digital converter (TDC) with gain calibration minimizes both the in-band phase noise degradation and the loop-bandwidth variation. In addition, a coarse-DPLL is introduced with dead-zone function, which reduces the phase lock time to 4.2 $\mu \text{s}$ at a 13-MHz frequency error. The coarse-DPLL monitors large frequency and phase jump in the background while consuming almost zero power. In an ultralow power mode, the proposed fractional- ${N}$ ADPLL consumes a 0.65-mW power with a 26-MHz reference. A rms jitter of 1.00 ps and −50-dBc in-band fractional spur are achieved with a −242-dB FOM. In high-performance mode, a reference doubler is utilized, the jitter and spurs can be improved to 535 fs and −56 dBc, respectively, while consuming 0.98 mW. The proposed ADPLL with scalable power and jitter performance can be utilized for Internet-of-Things (IoT) applications, such as Bluetooth low energy (BLE) and Wi-Fi networks.

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A Sub-mW Fractional- ${N}$ ADPLL With FOM of −246 dB for IoT Applications

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS

Precision oscillators are ubiquitous in modern electronic systems, and their accuracy often limits the performance of such systems Hence, a deep understanding of how oscillator performance is quantified, simulated, and measured, and how it affects the system performance is essential for designers Unfortunately, the necessary information is spread thinly across the published literature and textbooks with widely varying notations and some critical disconnects This paper addresses this problem by presenting a comprehensive one-stop explanation of how oscillator error is quantified, simulated, and measured in practice, and the effects of oscillator error in typical oscillator applications

https://ieeexplore.ieee.org/ielaam/8919/8566198/8449324-aam.pdf

Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement

A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137- and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a frequency multiplication ratio of 207.0019231 [digitally controlled oscillator (DCO) frequency is 50 kHz away from an integer multiple of the 26-MHz reference clock], a −78.6-dBc fractional spur is achieved for an output clock that runs at half of the DCO frequency. Time-to-digital converter (TDC) chopping technique, TDC fine conversion through successive approximation register analog-to-digital converters (SARADCs), and TDC nonlinearity calibration improve integrated phase noise and fractional spurs. This design meets the performance requirement of the 256-QAM $4 \times 4$ MIMO LTE standard in 5-GHz ISM band and also the 5G cellular 64-QAM standard in 28-GHz band. This work, implemented in a 14-nm fin-shaped field effect transistor (FinFET) CMOS process, is integrated to a cellular RF integrated circuit supporting advanced carrier aggregation operation. This PLL draws 13.4 mW and occupies 0.257 mm2.

A 14-nm 0.14-ps rms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

A sigma-delta fractional-N phase locked loop has faster lock time with increased charge pump current and decreased loop filter resistance in the unlock state. On the other hand, the sigma-delta fractional-N phase locked loop has lower noise susceptibility and lower frequency error with gradual decrease in charge pump current and gradual increase in loop filter resistance, in the lock state.

Sigma-delta fractional-N PLL with reduced frequency error

A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.

Frequency divider, frequency synthesizer and application circuit

A cascode bipolar low-noise amplifier (LNA) with capacitive shunt feedback has been developed to present a solution for simultaneous noise and power match when the real part of the optimum source impedance is not 50 Ω in order to keep high current density under power constraint. The proposed LNA also has the capability for the simultaneous improvement of noise figure (NF) and linearity. In addition, we analyzed and verified that the second-order interaction, which affects the third-order nonlinearity, becomes less sensitive to the low-frequency input termination at higher bias currents. The possibility of removing the low-frequency LC trap is investigated based on this analysis. We also show that LNAs with smaller base and/or smaller emitter resistances require lower source impedance at low frequencies to improve linearity by the same amount. Finally, prudent layouts for improving the performance of the LNA are considered. Eleven design examples of the proposed LNA, which individually operate at 880, 1575, or 1960 MHz, are fabricated in a low-cost 0.35- μm SiGe BiCMOS process to verify the design and analysis experimentally. The fabricated LNAs have excellent performances, especially in NF. For example, the 880-MHz LNA has an NF of 0.9 dB, a power gain of 16 dB, and an IIP3 of +14 dBm with current consumption of 11 mA from a 2.8-V power supply.

Design and Analysis of a Cascode Bipolar Low-Noise Amplifier With Capacitive Shunt Feedback Under Power-Constraint

A radar system using a quadrature signal includes a quadrature push—push oscillator for generating four harmonics with a 90-degree phase difference from each other, and producing two-balanced 2 nd harmonic signals from the harmonics; a first coupler block for radiating one of the 2 nd harmonics through an antenna; a second coupler block for terminating the other 2 nd harmonic to ground; and a power combiner for combining a transmitted signal that is leaked from the first and second coupler blocks with the received signal that is radiated through the antenna. The radar system features an improved receiving sensitivity by offsetting the leakage signals of the sending end. Also, the radar system can be made very small by using a single antenna for transmitting and receiving.

Sangsoo Ko

Papers

A 14-nm 0.14-ps rms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration

Sigma-delta fractional-N PLL with reduced frequency error

Frequency divider, frequency synthesizer and application circuit

Design and Analysis of a Cascode Bipolar Low-Noise Amplifier With Capacitive Shunt Feedback Under Power-Constraint

Radar system using quadrature signal