Sang Won Son

TL;DR: The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur.

TL;DR: Time-to-digital converter (TDC) chopping technique, TDC fine conversion through successive approximation register analog- to-digital converters (SARADCs), and TDC nonlinearity calibration improve integrated phase noise and fractional spurs.

TL;DR: The TX can be configured to provide better than -65 dBc CIM3, allowing it to meet stringent spurious emission specifications when transmitting 1 RB 4G LTE signals in B13/B26/B1, while demonstrating above 80 dB of gain control range.

TL;DR: In this article, a 6GHz fractional-N phase-locked loop (PLL) with a DTC range-reduction technique is presented. But the DTC also contributes to the in-band phase noise (PN) and its nonlinearity increases the fractional spur and noise folding.

TL;DR: A TDC chopping technique, fine-conversion through SARADCs and TDC nonlinearity calibration to improve IPN and fractional spurs are introduced and a digital fractional-N PLL is presented.