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Chih-Wei Yao
Researcher at Samsung
Publications - 13
Citations - 191
Chih-Wei Yao is an academic researcher from Samsung. The author has contributed to research in topics: Jitter & Phase-locked loop. The author has an hindex of 6, co-authored 13 publications receiving 122 citations.
Papers
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Journal ArticleDOI
A 28-nm 75-fs rms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
Wanghua Wu,Chih-Wei Yao,Kunal Godbole,Ronghua Ni,Pei-Yuan Chiang,Yongping Han,Yongrong Zuo,Ashutosh Verma,Ivan Siu-Chuang Lu,Sang Won Son,Thomas Byunghak Cho +10 more
TL;DR: The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur.
Journal ArticleDOI
A 14-nm 0.14-ps rms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration
Chih-Wei Yao,Ronghua Ni,Chung Lau,Wanghua Wu,Kunal Godbole,Yongrong Zuo,Sangsoo Ko,Nam-Seog Kim,Sang-Wook Han,Ikkyun Jo,Joon-hee Lee,Juyoung Han,Daehyeon Kwon,Chul-Ho Kim,Shinwoong Kim,Sang Won Son,Thomas Byunghak Cho +16 more
TL;DR: Time-to-digital converter (TDC) chopping technique, TDC fine conversion through successive approximation register analog- to-digital converters (SARADCs), and TDC nonlinearity calibration improve integrated phase noise and fractional spurs.
Proceedings ArticleDOI
21.6 A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS
Jongwoo Lee,Sang-Wook Han,Joon-hee Lee,Byoungjoong Kang,Jeong-Yeol Bae,Jaehyuk Jang,Seunghyun Oh,Suseob Ahn,Sanghoon Kang,Quang-Diep Bui,Kiyong Son,Hyung-sun Lim,Daechul Jeong,Ronghua Ni,Yongrong Zuo,Il-Yong Jong,Chih-Wei Yao,Seungchan Heo,Thomas Byunghak Cho,Inyup Kang +19 more
TL;DR: This paper demonstrates an integrated CMOS RFIC that supports multimode and multiband applications including all the legacy 2G, 3G, 4G and stand-alone/non-stand-alone sub-6GHz 5G NR features.
Proceedings ArticleDOI
24.8 A 14nm fractional-N digital PLL with 0.14ps rms jitter and −78dBc fractional spur for cellular RFICs
Chih-Wei Yao,Wing-Fai Loke,Ronghua Ni,Yongping Han,Haoyang Li,Kunal Godbole,Yongrong Zuo,Sangsoo Ko,Nam-Seog Kim,Sang-Wook Han,Ikkyun Jo,Joon-hee Lee,Juyoung Han,Daehyeon Kwon,Chul-Ho Kim,Shinwoong Kim,Sang Won Son,Thomas Byunghak Cho +17 more
TL;DR: A TDC chopping technique, fine-conversion through SARADCs and TDC nonlinearity calibration to improve IPN and fractional spurs are introduced and a digital fractional-N PLL is presented.
Patent
System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to- digital converter (TDC)
Wing-Fai Loke,Chih-Wei Yao +1 more
TL;DR: In this article, an analog-to-digital converter (ADC) driver was coupled to a ring oscillator, where the ADC output is coupled to the ring oscillators.