Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.

http://chialvo.org/Curso/UBACurso/DIA7/Papers/Aono_NatMat_07_Ionic%20Switching%20Memory.pdf

Nanoionics-based resistive switching memories

It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions.

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

The great variability in the electrical properties of multinary oxide materials, ranging from insulating, through semiconducting to metallic behaviour, has given rise to the idea of modulating the electronic properties on a nanometre scale for high-density electronic memory devices. A particularly promising aspect seems to be the ability of perovskites to provide bistable switching of the conductance between non-metallic and metallic behaviour by the application of an appropriate electric field. Here we demonstrate that the switching behaviour is an intrinsic feature of naturally occurring dislocations in single crystals of a prototypical ternary oxide, SrTiO(3). The phenomenon is shown to originate from local modulations of the oxygen content and to be related to the self-doping capability of the early transition metal oxides. Our results show that extended defects, such as dislocations, can act as bistable nanowires and hold technological promise for terabit memory devices.

Switching the electrical resistance of individual dislocations in single-crystalline SrTiO3

On the road towards higher memory density and computer performance, a significant improvement in energy efficiency constitutes the dominant goal in future information technology. Passive crossbar arrays of memristive elements were suggested a decade ago as non-volatile random access memories (RAM) and can also be used for reconfigurable logic circuits. As such they represent an interesting alternative to the conventional von Neumann based computer chip architectures. Crossbar architectures hold the promise of a significant reduction in energy consumption because of their ultimate scaling potential and because they allow for a local fusion of logic and memory, thus avoiding energy consumption by data transfer on the chip. However, the expected paradigm change has not yet taken place because the general problem of selecting a designated cell within a passive crossbar array without interference from sneak-path currents through neighbouring cells has not yet been solved satisfactorily. Here we introduce a complementary resistive switch. It consists of two antiserial memristive elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption.

Complementary resistive switches for passive nanocrossbar memories

Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (∼10−8 W) to massive data centers (∼109 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces. 
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/pdf/energy-dissipation-and-transport-in-nanoscale-devices-2fj1ezlyhz.pdf

Energy dissipation and transport in nanoscale devices

The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is accelerating introduction of new technologies to extend complementary MOS (CMOS) down to, and perhaps beyond, the 22-nm node This acceleration simultaneously requires the industry to intensify research on two highly challenging thrusts: one is scaling CMOS into an increasingly difficult manufacturing domain well below the 90-nm node for high performance (HP), low operating power (LOP), and low standby power (LSTP) applications, and the other is an exciting opportunity to invent fundamentally new approaches to information and signal processing to sustain functional scaling beyond the domain of CMOS This article is focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures This paper provides a brief introduction to each of the new nonclassical CMOS structures This is followed by a presentation of one scenario for introduction of new structural changes to the MOSFET to scale CMOS to the end of the ITRS A brief review of electrostatic scaling of a MOSFET necessary to manage short channel effects (SCEs) at the most advanced technology nodes is also provided

The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

The accelerating pace of CMOS scaling is rapidly approaching the fundamental limits of MOSFET performance, even as the projected size of a high-performance and manufacturable MOSFET technology is currently being extended with growing confidence to the 22-nm node (featuring a 9-nm physical gate length). The new 2001 International Technology Roadmap for Semiconductors currently projects the industry to reach this node in 2016. However, this forecast assumes the traditional industry node-cycle cadence of a quadrupling of the number of transistors every three years for DRAMS and a return to the three-year cycle in 2004 for MPUs and ASICs. During the past several years the node cycles for MPUs have been accelerated to occur within two-year periods. This pace will bring the microelectronics industry to the end of silicon CMOS technology scaling sometime not later than 2016, and maybe as soon as 2010. The new Emerging Technologies section of the 2001 ITRS offers guidance on both sides of this problem: nanoelectronics for memory, logic, and information-processing architectures could possibly extend the time frame of the ITRS beyond CMOS.

Extending the road beyond CMOS

Presents an an assessment of new field-effect transistor, resonant tunnel device, single-electron transistor and quantum cellular automata technologies. The goal of this article is to provide technical assessments of new logic technologies. We attempt to "cast a broad net" to gather in one place alternative concepts for logic that would, if successful, substantially extend the International Technology Roadmap for Semiconductors (ITRS) beyond CMOS. The discussions provide some detail regarding device operation principles, advantages, challenges, maturity, and current and projected performance. The scaling of CMOS device and process technology, as it is known today, is projected to continue (7-nm physical channel length) by 2019. The grand challenge, then, is to invent and develop one or more new technologies that will extend the scaling of information-processing technologies through multiple generations beyond 2019. Such new technologies must meet certain fundamental requirements and possess certain compelling attributes to justify the very substantial investments that are necessary to build a new infrastructure.

Emerging research logic devices

The search for alternate information processing technologies to sustain Moore's Law improvements beyond those attainable by scaling of charge-based devices encompasses several key technologies. Some of these technologies were explored at the Third Workshop on Silicon Nanoelectronics and Beyond (SNB III) held at the National Science Foundation in Washington DC in December 2005. They included: (1) non-charge-based devices; (2) devices operated out of thermal equilibrium; (3) alternative interconnect systems; (4) thermal extraction limits and technologies; and (5) fabrication via directed self-assembly. Although this paper was inspired by this highly successful workshop, it is not intended as a summary, but rather an assessment by the authors of some of the fundamental physical considerations evident at the present time.

/pdf/research-directions-and-challenges-in-nanoelectronics-2olmkwg46v.pdf

J.A. Hutchby

Papers

The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

Extending the road beyond CMOS

Emerging research logic devices

Research directions and challenges in nanoelectronics

Emerging nanoelectronic devices