Journal ArticleDOI
The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance
TLDR
In this article, the authors focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures using new non-classical CMOS structures.Abstract:
The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is accelerating introduction of new technologies to extend complementary MOS (CMOS) down to, and perhaps beyond, the 22-nm node This acceleration simultaneously requires the industry to intensify research on two highly challenging thrusts: one is scaling CMOS into an increasingly difficult manufacturing domain well below the 90-nm node for high performance (HP), low operating power (LOP), and low standby power (LSTP) applications, and the other is an exciting opportunity to invent fundamentally new approaches to information and signal processing to sustain functional scaling beyond the domain of CMOS This article is focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures This paper provides a brief introduction to each of the new nonclassical CMOS structures This is followed by a presentation of one scenario for introduction of new structural changes to the MOSFET to scale CMOS to the end of the ITRS A brief review of electrostatic scaling of a MOSFET necessary to manage short channel effects (SCEs) at the most advanced technology nodes is also providedread more
Citations
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Journal ArticleDOI
Evolution of Block Copolymer Lithography to Highly Ordered Square Arrays
TL;DR: This work presents a modular and hierarchical self-assembly strategy, combining supramolecular assembly of hydrogen-bonding units with controlled phase separation of diblock copolymers, for the generation of nanoscale square patterns that will enable simplified addressability and circuit interconnection in integrated circuit manufacturing and nanotechnology.
Journal ArticleDOI
Improved Contacts to MoS2 Transistors by Ultra-High Vacuum Metal Deposition
TL;DR: A systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition conditions, over a wide range of temperatures, carrier densities, and contact dimensions finds that Au deposited in ultra-high vacuum yields three times lower RC than under normal conditions.
Journal ArticleDOI
Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches
Chenguang Qiu,Fei Liu,Lin Xu,Bing Deng,Mengmeng Xiao,Jia Si,Li Lin,Zhiyong Zhang,Jian Wang,Hong Guo,Hailin Peng,Lian-Mao Peng +11 more
TL;DR: It is shown that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower subthreshold swing and supply voltage in field-effect transistors.
Journal ArticleDOI
Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia
Thomas Skotnicki,Claire Fenouillet-Beranger,C. Gallon,F. Buf,Stephane Monfray,F. Payet,A. Pouydebasque,M. Szczap,Alexis Farcy,Franck Arnaud,Sylvain Clerc,M. Sellier,A. Cathignol,Jean-Pierre Schoellkopf,E. Perea,R. Ferrant,H. Mingam +16 more
TL;DR: In this article, a detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented, along with the state of the art, requirements, and solutions at the level of materials, transistor, and technology.
Proceedings ArticleDOI
Why is CMOS scaling coming to an END
Nor Zaidi Haron,Said Hamdioui +1 more
TL;DR: This paper discusses and analyzes the main challenges and limitations of CMOS scaling, not only from physical and technological point of view, but also from material (e.g., high-k vs. low-k) and economical points of view as well.
References
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Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Proceedings ArticleDOI
FinFET scaling to 10 nm gate length
Bin Yu,Leland Chang,Shibly S. Ahmed,Haihong Wang,Scott A. Bell,Chih-Yuh Yang,Cyrus E. Tabery,Chau M. Ho,Qi Xiang,Tsu-Jae King,Jeffrey Bokor,Chenming Hu,Ming-Ren Lin,D. Kyser +13 more
TL;DR: In this paper, the authors report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm.
Journal ArticleDOI
A logic nanotechnology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,S. Cea,R. Chau,G. Glass,T. Hoffman,Jason Klaus,Z. Ma,B. McIntyre,Anand Portland Murthy,B. Obradovic,Lucian Shifren,Swaminathan Sivakumar,S. Tyagi,Tahir Ghani,Kaizad Mistry,Mark T. Bohr,Y. El-Mansy +18 more
TL;DR: In this article, a tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility.
Journal ArticleDOI
High performance fully-depleted tri-gate CMOS transistors
Brian S. Doyle,Suman Datta,Mark Beaverton Doczy,Scott Hareland,B. Jin,Jack Portland Kavalieros,Thomas D. Linton,Anand Portland Murthy,Rafael Rios,R. Chau +9 more
TL;DR: Fully depleted tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated in this article, where the transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages.