H
Hon-Sum Philip Wong
Researcher at Stanford University
Publications - 213
Citations - 18292
Hon-Sum Philip Wong is an academic researcher from Stanford University. The author has contributed to research in topics: Field-effect transistor & CMOS. The author has an hindex of 64, co-authored 212 publications receiving 17148 citations. Previous affiliations of Hon-Sum Philip Wong include IBM & Lehigh University.
Papers
More filters
Journal ArticleDOI
Metal–Oxide RRAM
Hon-Sum Philip Wong,Heng-Yuan Lee,Shimeng Yu,Yu-Sheng Chen,Yi Wu,Pang-Shiu Chen,Byoungil Lee,Frederick T. Chen,Ming-Jinn Tsai +8 more
TL;DR: The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide resistive switching random access memory (RRAM) are discussed, with a focus on the use of RRAM for nonvolatile memory application.
Journal ArticleDOI
Device scaling limits of Si MOSFETs and their application dependencies
TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Journal ArticleDOI
CMOS scaling into the nanometer regime
Yuan Taur,Douglas A. Buchanan,Wei Chen,David J. Frank,Khalid EzzEldin Ismail,Shih-Hsien Lo,George Anthony Sai-Halasz,R. Viswanathan,Hsing-Jen Wann,Shalom J. Wind,Hon-Sum Philip Wong +10 more
TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.
Journal ArticleDOI
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region
Jie Deng,Hon-Sum Philip Wong +1 more
TL;DR: In this paper, a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field effect transistors (CNFETs) is presented.
Journal ArticleDOI
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking
Jie Deng,Hon-Sum Philip Wong +1 more
TL;DR: In this paper, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE, including elastic scattering in the channel region, resistive source/drain (S/D), Schottky-barrier resistance, and parasitic gate capacitances.