Neuromorphic computing takes inspiration from the brain to create energy-efficient hardware for information processing, capable of highly sophisticated tasks. Systems built with standard electronics achieve gains in speed and energy by mimicking the distributed topology of the brain. Scaling-up such systems and improving their energy usage, speed and performance by several orders of magnitude requires a revolution in hardware. We discuss how including more physics in the algorithms and nanoscale materials used for data processing could have a major impact in the field of neuromorphic computing. We review striking results that leverage physics to enhance the computing capabilities of artificial neural networks, using resistive switching materials, photonics, spintronics and other technologies. We discuss the paths that could lead these approaches to maturity, towards low-power, miniaturized chips that could infer and learn in real time. Neuromorphic computing takes inspiration from the brain to create energy-efficient hardware for information processing, capable of highly sophisticated tasks. Including more physics in the algorithms and nanoscale materials used for computing could have a major impact in this field.

Physics for neuromorphic computing

Artificial intelligence (AI) has the ability of revolutionizing our lives and society in a radical way, by enabling machine learning in the industry, business, health, transportation, and many other fields. The ability to recognize objects, faces, and speech, requires, however, exceptional computational power and time, which is conflicting with the current difficulties in transistor scaling due to physical and architectural limitations. As a result, to accelerate the progress of AI, it is necessary to develop materials, devices, and systems that closely mimic the human brain. In this work, we review the current status and challenges on the emerging neuromorphic devices for brain-inspired computing. First, we provide an overview of the memory device technologies which have been proposed for synapse and neuron circuits in neuromorphic systems. Then, we describe the implementation of synaptic learning in the two main types of neural networks, namely the deep neural network and the spiking neural network (SNN). Bio-inspired learning, such as the spike-timing dependent plasticity scheme, is shown to enable unsupervised learning processes which are typical of the human brain. Hardware implementations of SNNs for the recognition of spatial and spatio-temporal patterns are also shown to support the cognitive computation in silico. Finally, we explore the recent advances in reproducing bio-neural processes via device physics, such as insulating-metal transitions, nanoionics drift/diffusion, and magnetization flipping in spintronic devices. By harnessing the device physics in emerging materials, neuromorphic engineering with advanced functionality, higher density and better energy efficiency can be developed.

https://iopscience.iop.org/article/10.1088/1361-6528/ab554b/pdf

Emerging neuromorphic devices.

In this review the different concepts of nanoscale resistive switching memory devices are described and classified according to their I-V behaviour and the underlying physical switching mechanisms. By means of the most important representative devices, the current state of electrical performance characteristics is illuminated in-depth. Moreover, the ability of resistive switching devices to be integrated into state-of-the-art CMOS circuits under the additional consideration with a suitable selector device for memory array operation is assessed. From this analysis, and by factoring in the maturity of the different concepts, a ranking methodology for application of the nanoscale resistive switching memory devices in the memory landscape is derived. Finally, the suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed.

https://iopscience.iop.org/article/10.1088/1361-6528/ab2084/pdf

Nanoscale resistive switching memory devices: a review.

Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in hardware accelerator design for deep learning. The input vector and weight matrix multiplication, i.e., the multiply-and-accumulate (MAC) operation, could be performed in the analog domain within memory sub-array, leading to significant improvements in throughput and energy efficiency. Static random access memory (SRAM) and emerging non-volatile memories such as resistive random access memory (RRAM) are promising candidates to store the weights of deep neural network (DNN) models. In this review, firstly we survey the recent progresses in SRAM and RRAM based CIM macros that have been demonstrated in silicon. Then we discuss general design challenges of the CIM chips including analog-to-digital conversion (ADC) bottleneck, variations in analog compute, and device non-idealities. Next we introduce the DNN+NeuroSim benchmark framework that is capable of evaluating versatile device technologies for CIM inference and training performance from software/hardware co-design's perspective.

Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects

Neuromorphic computing takes inspiration from the brain to create energy efficient hardware for information processing, capable of highly sophisticated tasks. In this article, we make the case that building this new hardware necessitates reinventing electronics. We show that research in physics and material science will be key to create artificial nano-neurons and synapses, to connect them together in huge numbers, to organize them in complex systems, and to compute with them efficiently. We describe how some researchers choose to take inspiration from artificial intelligence to move forward in this direction, whereas others prefer taking inspiration from neuroscience, and we highlight recent striking results obtained with these two approaches. Finally, we discuss the challenges and perspectives in neuromorphic physics, which include developing the algorithms and the hardware hand in hand, making significant advances with small toy systems, as well as building large scale networks.

Physics for Neuromorphic Computing

For the first time we propose a 28nm FDSOI e-NVM solution for automotive micro-controller applications using a Phase Change Memory (PCM) based on chalcogenide ternary material. A complete array organization is described exploiting body biasing capability of Fully Depleted Silicon On Insulator (FDSOI) transistors. Leveraging triple gate oxide integration with high-k metal gate (HKMG) stack, a true 5V transistor with high analog performance has been demonstrated. Reliable PCM 0,036um2 analytical cell with 2 decades programming window after 1 Million of cycles has been demonstrated. Finally, current distributions based on a fully integrated 16MB macro-cell is presented achieving Bit Error Rate (BER) < 10−8 after multiple bakes at 150°C and 10k cycling of code storage memory.

Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory

in this paper we present an enhancement of our 28nm FDSOI-PCM solution using Bipolar Junction Transistor (BJT) selector co-integrated with triple gate oxide devices scheme (logic/1,8V/5V) for advanced automotive microcontroller designs. Leveraging FDSOI substrate, innovative Super-STI (SSTI) scheme has been developed enabling 0,019um2 PCM cell. It is the densest eNVM cell reported so far, based on our knowledge. Ultimate analog performance targets for automotive have been successfully demonstrated without compromising reliability for 5V transistor thanks to a novel gate stack & spacers architecture. Automotive grade-0 reliability criteria have been achieved on 16MB PCM array, including 3x aggressive runs of soldering reflow thermal stress (265°C/210s). Finally, wide reading window has been shown even after 250K writing operation at 165°C.

High Density Embedded PCM Cell in 28nm FDSOI Technology for Automotive Micro-Controller Applications

The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the first part of the paper. A new metric for quantification of active material modifications is introduced to better follow its evolution with process sequence. Ge clustering has been shown to occur during the fabrication, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is identified, and an extensive electrical characterization of array performance and reliability is done on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

J. C. Grenier

Papers

Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory

High Density Embedded PCM Cell in 28nm FDSOI Technology for Automotive Micro-Controller Applications

BEOL Process Effects on ePCM Reliability